6771645678
Additional UPDs included with FSP 2.5.0:
FspsUpd.h:
*SataRstOptaneMemory
*Additional Upds for Core Ratio limit
FspmUpd.h:
*RingDownBin
*PcdDebugInterfaceFlags
*PcdSerialDebugBaudRate
*PcdSerialDebugLevel
*GtPllVoltageOffset
*RingPllVoltageOffset
*SaPllVoltageOffset
*McPllVoltageOffset
*RealtimeMemoryTiming
*EvLoader
*Avx3RatioOffset
CQ-DEPEND=CL:*388108,CL:*388109
BUG=None
BRANCH=None
TEST=Build and test on Soraka
Signed-off-by: Balaji Manigandan B <balaji.manigandan@intel.com>
Change-Id: Id31ddd4595e36c91ba7c888688114c4dbe4db86a
Reviewed-on: https://review.coreboot.org/20123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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| intel | ||
| siemens | ||
| Makefile.inc | ||