coreboot/src
Kyösti Mälkki e079e5ccc2 device/pci_ops: Inline PCI config accessors for ramstage
Inlining here allows the check for (dev != NULL) to be
optimised and evaluated just once inside the calling
function body.

Change-Id: I0b5b4f4adb8eaa483a31353324da19917db85f4a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-06 11:53:56 +00:00
..
acpi
arch device/pci_ops: Change ramstage PCI accessor signatures 2019-03-06 11:44:06 +00:00
commonlib device/mmio.h: Add include file for MMIO ops 2019-03-04 15:57:39 +00:00
console arch/io.h: Separate MMIO and PNP ops 2019-03-04 15:59:23 +00:00
cpu x86/car: Fix incorrect config usage 2019-03-06 01:14:57 +00:00
device device/pci_ops: Inline PCI config accessors for ramstage 2019-03-06 11:53:56 +00:00
drivers device/mmio.h: Add include file for MMIO ops 2019-03-04 15:57:39 +00:00
ec device/pnp: Add header files for PNP ops 2019-03-04 15:58:55 +00:00
include device/pci_ops: Inline PCI config accessors for ramstage 2019-03-06 11:53:56 +00:00
lib mb/qemu-{i440fx,q35}: Use POSTCAR stage to load the ramstage 2019-03-05 19:35:37 +00:00
mainboard mainboard: Enable PRESERVE flag in all vboot/chromeos FMD files 2019-03-05 20:52:06 +00:00
northbridge device/mmio.h: Add include file for MMIO ops 2019-03-04 15:57:39 +00:00
security console: Refactor printk() varargs prototypes 2019-02-27 11:09:31 +00:00
soc soc/intel: Use simple PCI config access 2019-03-06 11:38:20 +00:00
southbridge sb/amd: Use simple PCI IO config access 2019-03-06 11:38:10 +00:00
superio superio/ite/it8613e: add support for ITE IT8613E 2019-03-06 11:27:49 +00:00
vendorcode device/mmio.h: Add include file for MMIO ops 2019-03-04 15:57:39 +00:00
Kconfig Kconfig: Add system type entries for common enclosures 2019-02-05 16:03:29 +00:00