Add DisableHeciRetry to the chip config and parse it in romstage. Change-Id: I460b51834c7de42e68fe3d54c66acd1022a3bdaf Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> |
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| .. | ||
| apollolake | ||
| baytrail | ||
| braswell | ||
| broadwell | ||
| cannonlake | ||
| common | ||
| denverton_ns | ||
| icelake | ||
| jasperlake | ||
| quark | ||
| skylake | ||
| tigerlake | ||
| xeon_sp | ||
| Kconfig | ||