coreboot/src/vendorcode/amd
Matt DeVillier d77525b5bd vc/amd/fsp/mendocino: Update DMI_T17_MEMORY_TYPE
Synchronize with AGESA/AgesaModulePkg/Include/MemDmi.h.
Add/correct values for DDR5, LPDDR5, LPDDR5X.

BUG=b:239000826
TEST=Build and verify with other patches in train

Change-Id: I127f21bfe2dfcd7794eb543185ea3fb362ff3914
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-08-24 15:14:15 +00:00
..
agesa vc/amd/agesa/f15tn: Declare value as constant in GnbRegisterWriteTNDump() 2022-06-08 16:21:59 +00:00
cimx vendorcode/amd/cimx/sb900: Drop code 2022-05-11 05:59:06 +00:00
fsp vc/amd/fsp/mendocino: Update DMI_T17_MEMORY_TYPE 2022-08-24 15:14:15 +00:00
include treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
pi amd/*/gcccar.inc: Replace local declarations 2022-05-11 13:55:18 +00:00
Kconfig vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles 2020-12-02 17:05:39 +00:00
Makefile.inc AMD Steppe Eagle: Add binary PI vendorcode files 2014-08-30 19:13:45 +02:00