coreboot/src/soc/intel
Alexandru Gagniuc dfc2b31517 soc/apollolake: Add initial cache-as-ram setup for bootblock
This is the minimum setup needed to both get cache-as-ram setup and a
C environment working. On apollolake, we only get 32 KiB of data
loaded into an SRAM that is readonly to the main CPU. Due to this
restriction we have to set CAR and a C environment very early on.

Change-Id: I65c51f972580609d2c1f03dfe2a86bc5d45d1e46
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13301
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-02-11 21:00:07 +01:00
..
apollolake soc/apollolake: Add initial cache-as-ram setup for bootblock 2016-02-11 21:00:07 +01:00
baytrail ACPI: Fix IASL Warning about unused method for GBUF check 2015-12-10 16:30:50 +01:00
braswell drivers/intel/fsp1_1: Fix spelling error in API and copyright 2016-01-31 20:51:29 +01:00
broadwell chromeos: Remove CONFIG_VBNV_SIZE variable 2016-02-09 13:19:48 +01:00
common soc/intel/common: Use SoC specific routine to read/write MTRRs 2016-02-02 19:00:35 +01:00
fsp_baytrail soc/fsp_baytrail: Add support for FSP MR 005 2016-02-10 02:45:56 +01:00
quark soc/intel/quark: Report CPU info 2016-02-10 03:12:18 +01:00
skylake Kconfig: Move defaults for CBFS_SIZE 2016-02-10 16:27:50 +01:00