coreboot/src/cpu
Patrick Rudolph de8e4d930d cpu/x86/64bit/mode_switch: Work around FSP bug
FSP, that is build against EDK2 2018 or newer, is able to back up and
restore the bootloader IDT on entry/exit. Even though it sets up its
own IDT, FSP checks the bootloader IDT size and deadloops without
warning if it's too big.

On x86_64 coreboot the IDT is naturally bigger than on x86_32 and thus
x86_32 FSP might die on entry. Work around this issue by:

* Back up and restore the IDT in protected_mode_call_wrapper
* Load zero IDT in protected mode before jumping to function

TEST: Can boot on SPR FSP (x86_32) using x86_64 coreboot with
      exceptions in romstage enabled.

Change-Id: I56367d8153aa10a9b1bcaa5ffde8ebe202e8c00c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85789
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2025-01-08 08:17:57 +00:00
..
amd treewide: Remove unused CHIPs 2024-02-20 11:01:36 +00:00
armltd arch to cpu: Add SPDX license headers to Kconfig files 2024-02-18 01:58:52 +00:00
intel cpu/intel/car/romstage: Fix false-positive stack corruption 2024-12-17 17:36:47 +00:00
power9 include/device/device.h: Remove CHIP_NAME() macro 2024-01-31 09:51:58 +00:00
qemu-power8 include/device/device.h: Remove CHIP_NAME() macro 2024-01-31 09:51:58 +00:00
qemu-x86 cpu/qemu: Enable IDT_IN_EVERY_STAGE 2024-12-17 17:37:54 +00:00
via cpu/via/c7: Compress ramstage with LZ4 by default 2024-11-21 09:26:17 +00:00
x86 cpu/x86/64bit/mode_switch: Work around FSP bug 2025-01-08 08:17:57 +00:00
Kconfig arch to cpu: Add SPDX license headers to Kconfig files 2024-02-18 01:58:52 +00:00
Makefile.mk via: Start template for VIA C7 w/ CX700 northbridge 2024-11-11 09:16:55 +00:00