Felix Held dd882f3812 soc/amd/cezanne/root_complex: generate DPTC ACPI method ... This adds support for convertible devices to support different maximum power and thermal configurations. The dynamic power and thermal configuration (DPTC) via ACPI ALIB calls allows to change the parameters during runtime. This code contains the assumption that \_SB.PCI0.LPCB.EC0.TBMD exists when ACPI code calls the DPTC method. At the moment only chromeec declares EC0.TBMD, but it's also the only code that calls the DPTC method. The definition of DPTC_INPUTS isn't moved to the common code directory, since it's currently unsure if we might need to configure more than those 4 parameters for Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibdfc056cb325a32d87505dd93e01c9af81dfd6c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>		2021-05-13 00:58:17 +00:00
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cezanne	soc/amd/cezanne/root_complex: generate DPTC ACPI method	2021-05-13 00:58:17 +00:00
common	psp_verstage: remove not-implemented files for cezanne	2021-05-12 15:16:56 +00:00
picasso	soc/amd/{common,picasso}: Use common PCIE_GPP_DRIVER driver	2021-05-12 00:46:27 +00:00
stoneyridge	soc/amd: factor out ACPI ALIB function numbers to common code	2021-05-08 17:56:10 +00:00
Kconfig	soc/amd: rename common Kconfig and use wildcard for SoC-specific Kconfig	2020-11-19 14:29:14 +00:00