coreboot/src/arch
Jonathan Neuschäfer fb0699a9ec UPSTREAM: arch/riscv: Fix the page table setup code
In particular:

- Fix the condition of the loop that fills the mid-level page table
- Adhere to the format of sptbr

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16120
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

Change-Id: I575093445edfdf5a8f54b0f8622ff0e89f77ccec
Reviewed-on: https://chromium-review.googlesource.com/369148
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-15 07:35:56 -07:00
..
arm UPSTREAM: src/arch: Capitalize CPU, RAM and ROM 2016-08-04 23:37:18 -07:00
arm64 UPSTREAM: arm64: Add stack dump to exception handler 2016-05-26 03:21:55 -07:00
mips build system: remove CBFSTOOL_PRE1_OPTS 2016-05-03 11:40:49 +02:00
power8 UPSTREAM: region: Add writeat and eraseat support 2016-06-27 17:13:18 -07:00
riscv UPSTREAM: arch/riscv: Fix the page table setup code 2016-08-15 07:35:56 -07:00
x86 UPSTREAM: acpi: Generate object for coreboot table region 2016-08-12 13:45:10 -07:00