coreboot/src/northbridge
Angel Pons d5854e4139 Haswell NRI: Implement COMP offset optimisation
This algorithm minimises the per-channel, per-lane digital COMP offsets
by adjusting the global COMP offset accordingly. The purpose of this is
not fully known, but it is likely to prevent saturation of per-channel,
per-lane registers during subsequent training steps, which NRI does not
implement yet. Some of the COMP offset functions are generic since they
are also used in said training steps.

Tested on Asrock B85M Pro4, still boots to Arch Linux.

Change-Id: Idb03c6c5ed85a522ff1b55905f522211d1472bd9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87833
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2025-07-04 13:17:47 +00:00
..
amd nb/amd/pi/00730F01/northbridge: skip IVRS when IOMMU is disabled 2025-05-16 20:42:08 +00:00
intel Haswell NRI: Implement COMP offset optimisation 2025-07-04 13:17:47 +00:00
via/cx700 nb/via/cx700/romstage: Include missing static.h header 2024-11-21 12:25:19 +00:00