Edward O'Callaghan dd191a2a7d soc/intel/broadwell/spi_loading.c: Remove dead code ... I would appear from commit a6354a1 that this is now dead code. Change-Id: I0f74183c9a5d8cc6ff5a11409d487cc45d9ed2df Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8168 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>		2015-01-12 18:55:49 +01:00
..
arch	ACPI: Add acpi_is_wakeup_s3() for romstage	2015-01-10 13:53:51 +01:00
console	misc: Drop print_ implementation from non-romcc boards	2015-01-09 06:12:22 +01:00
cpu	ACPI: Add acpi_is_wakeup_s3() for romstage	2015-01-10 13:53:51 +01:00
device	doxygen fixes: fix parameter names to match the functions	2015-01-06 06:32:37 +01:00
drivers	elog: Add ELOG_TYPE_BOOT event using fake boot count if necessary	2015-01-09 07:46:56 +01:00
ec	chrome ec: Add ACPI Device for ALS if enabled	2015-01-09 07:43:34 +01:00
include	Primitive memory test	2015-01-09 16:50:55 +01:00
lib	Primitive memory test	2015-01-09 16:50:55 +01:00
mainboard	mainboard/lenovo/?/Kconfig: select NO_UART_ON_SUPERIO	2015-01-12 15:50:08 +01:00
northbridge	ACPI: Add acpi_is_wakeup_s3() for romstage	2015-01-10 13:53:51 +01:00
soc	soc/intel/broadwell/spi_loading.c: Remove dead code	2015-01-12 18:55:49 +01:00
southbridge	ACPI: Add acpi_is_wakeup_s3() for romstage	2015-01-10 13:53:51 +01:00
superio	superio: Drop print_ implementation from non-romcc boards	2015-01-06 20:14:19 +01:00
vendorcode	elog: Add function to log boot reason in ChromeOS case	2015-01-03 00:25:27 +01:00
Kconfig	Allow RISCV to be compiled with ANY_TOOLCHAIN	2015-01-02 18:44:57 +01:00