add back in empty stage chipset variable. It will be filled in later. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://coreboot.org/repository/coreboot-v3@736 f3766cd6-281f-0410-b1cd-43a5c92072e9 |
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