Maulik V Vaghela db9e9ac30d soc/intel/cannonlake: Add PCH series check for CML LP PCH ... TEST=Verify PM_STS1 value is is not 0xFF. Change-Id: I932585f6e7525830bd57ecfc372bf3120e7cca66 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/31434 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2019-02-28 09:26:01 +00:00
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apollolake	soc/intel: Add mem_rank info in SMBIOS	2019-02-18 20:25:42 +00:00
baytrail	security/vboot: Add measured boot mode	2019-02-25 22:29:16 +00:00
braswell	security/vboot: Add measured boot mode	2019-02-25 22:29:16 +00:00
broadwell	security/vboot: Add measured boot mode	2019-02-25 22:29:16 +00:00
cannonlake	soc/intel/cannonlake: Add PCH series check for CML LP PCH	2019-02-28 09:26:01 +00:00
common	soc/intel/cannonlake: Add Comet Lake U SA 2+2 Device ID	2019-02-28 02:22:11 +00:00
denverton_ns	soc/intel/denverton_ns: Add ACPI T-States and P-States	2019-01-28 13:33:30 +00:00
fsp_baytrail	security/vboot: Add measured boot mode	2019-02-25 22:29:16 +00:00
fsp_broadwell_de	security/vboot: Add measured boot mode	2019-02-25 22:29:16 +00:00
icelake	soc/intel: Add mem_rank info in SMBIOS	2019-02-18 20:25:42 +00:00
quark	console: Split loglevel for fast and slow	2019-02-27 11:10:00 +00:00
skylake	soc/intel/skylake: Remove redundant PM emulation timer macros	2019-02-28 02:21:44 +00:00
Kconfig	src/cpu: Remove dead sourced lines	2018-11-15 10:25:20 +00:00