Philipp Deppenwiese db70f3bb4d drivers/tpm: Add TPM ramstage driver for devices without vboot. ... Logic: If vboot is not used and the tpm is not initialized in the romstage makes use of the ramstage driver to initialize the TPM globally without having setup calls in lower SoC level implementations. * Add TPM driver in ramstage chip init which calls the tpm_setup function. * Purge all occurrences of TPM init code and headers. * Only compile TIS drivers into ramstage except for vboot usage. * Remove Google Urara/Rotor TPM support because of missing i2c driver in ramstage. Change-Id: I7536c9734732aeaa85ccc7916c12eecb9ca26b2e Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/24905 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2018-07-25 15:53:35 +00:00
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e7505	nb/intel/e7505: Leave ROM as un-cacheable in postcar	2018-06-20 19:00:07 +00:00
fsp_rangeley	src/northbridge: Use "foo *bar" instead of "foo* bar"	2018-07-09 09:29:53 +00:00
fsp_sandybridge	src/northbridge: Use "foo *bar" instead of "foo* bar"	2018-07-09 09:29:53 +00:00
gm45	src/northbridge: Use "foo *bar" instead of "foo* bar"	2018-07-09 09:29:53 +00:00
haswell	src/nb: Fix non-local header treated as local	2018-07-02 07:39:16 +00:00
i440bx	nb/intel/i440bx: Switch to POSTCAR_STAGE	2018-06-17 19:17:11 +00:00
i945	nb/i945/raminit: Correct C0DRAMW & C1DRAMW for 4 DIMMs	2018-07-12 11:52:52 +00:00
nehalem	src/northbridge: Use "foo *bar" instead of "foo* bar"	2018-07-09 09:29:53 +00:00
pineview	src/northbridge: Use "foo *bar" instead of "foo* bar"	2018-07-09 09:29:53 +00:00
sandybridge	drivers/tpm: Add TPM ramstage driver for devices without vboot.	2018-07-25 15:53:35 +00:00
x4x	sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tables	2018-06-29 07:45:30 +00:00