Duncan Laurie daf6d412cc broadwell: Enable double self refresh by default ... Rather than enable this in every mainboard just enable it by default for all broadwell devices and let a specific mainboard disable it if needed. BUG=chrome-os-partner:34420 BRANCH=samus,auron TEST=build and boot on samus Change-Id: I6e47c20abf29abfbd1f4b7905914b4c9fadb0ae7 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 25d3a685893e1c85f7b78e302da3187947a1f84f Original-Change-Id: I26d9f2e2a12d3f2f888ecb5af0d949eec5928f57 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/238400 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9590 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>		2015-04-13 12:19:25 +02:00
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arch	arch: armv7: Fix cache sync instructions.	2015-04-13 12:19:11 +02:00
console
cpu	vendorcode/amd/agesa/f16kb: Enable support for AM1 socket	2015-04-10 15:29:24 +02:00
device
drivers	TPM: Reduce buffer size to fix stack overflow	2015-04-10 20:06:23 +02:00
ec	samus: Log EC panics to eventlog	2015-04-10 20:32:26 +02:00
include	PCI - Add interrupt disable bit definition	2015-04-10 20:10:55 +02:00
lib	vboot: Include vb2_api.h, instead of lower-level vboot2 header files	2015-04-10 16:49:15 +02:00
mainboard	hp/pavilion_m6_1035dx/cmos.layout: Remove unused options	2015-04-11 21:51:51 +02:00
northbridge	northbridge/amd/agesa/familyXY: Make NULL device op explicit	2015-04-09 19:34:22 +02:00
soc	broadwell: Enable double self refresh by default	2015-04-13 12:19:25 +02:00
southbridge	southbridge/intel/fsp_rangeley/ : Spellcheck + Formatting	2015-04-10 17:57:11 +02:00
superio
vendorcode	vboot2: use offset to vboot2 work buffer instead of absolute address	2015-04-13 12:19:16 +02:00
Kconfig	cbtables: Add RAM config information	2015-04-10 16:47:44 +02:00