- C 93.8%
- ASL 2.2%
- Makefile 1.1%
- C++ 0.5%
- Pawn 0.5%
- Other 1.8%
Updating from commit id b68861c7298d: 2025-05-15 14:26:57 +0000 - (Merge "docs(changelog): add missing scopes" into integration) to commit id 9109143417b2: 2025-06-05 22:03:35 +0000 - (Merge "feat(cpus): update cpu_check_csv2 check" into integration) This brings in 55 new commits: 9109143417b2 Merge "feat(cpus): update cpu_check_csv2 check" into integration 470404b8b02f Merge "fix(xlat): change MT_DEVICE to map to nGnRnE" into integration 08b11700e781 Merge "fix(fvp): avoid stack usage in check_cpupwrctrl_el1_is_available()" into integration 2b43216593f1 feat(cpus): update cpu_check_csv2 check 36ceead86b06 fix(fvp): avoid stack usage in check_cpupwrctrl_el1_is_available() 9526ad605872 Merge changes from topic "st_fixes" into integration adbcd85eec11 Merge changes from topic "xlnx_versal_custom_sip" into integration a0aec93934cf Merge "fix(qemu): fix variable may be used uninitialized error" into integration 8681f772fb53 Merge "feat(intel): update CPUECTLR_EL1 to boost ethernet performance" into integration 4902381ac01a Merge "feat(mt8189): add IOMMU enable control in SiP service" into integration 02309a84fbfb Merge changes Ia29fd72f,I31b359ce,I1296aaff,I30e1ee7f,Ib4a3593e, ... into integration fbab861f7f73 Merge "feat(smcc): introduce a new vendor_el3 service for ACS SMC handler" into integration db0d5350af03 fix(qemu): fix variable may be used uninitialized error fe524532e345 Merge "docs(versal-net): update documentation for SDEI" into integration 0d003ff58d98 Merge "chore(fvp): remove unused macro definition" into integration bc11248abbcd Merge changes from topic "xlnx_versal_misra_fixes_series_3" into integration 236422ad7a17 Merge "fix(xilinx): resolve violations generated with IPI_CRC_CHECK enabled" into integration a335cd91179a fix(xilinx): resolve misra rule 16.3 violations 93db9e6161d5 fix(xilinx): resolve misra rule 2.5 violations 6df7184e5ae0 fix(xilinx): resolve misra rule 4.6 violations f78c597041fc fix(xilinx): resolve misra rule 12.2 violations 7d0eb0e1e544 fix(xilinx): resolve violations generated with IPI_CRC_CHECK enabled c314a0b3fe24 fix(xilinx): resolve misra rule 10.1 violations cd60ab793e22 fix(xilinx): resolve misra rule 8.13 violations 2993166d498b fix(xilinx): resolve misra rule 4.5 violations ea3ec86552d3 fix(xilinx): resolve misra rule 16.4 violations 00669dcd96b9 fix(xlat): change MT_DEVICE to map to nGnRnE 5be0e22591d7 feat(mt8196): add SMMU SID stub implementation e86fb819834f feat(mt8196): add SLBC SiP handler 4488b229e573 feat(mt8196): add CPU QoS stub implementation 001058820482 refactor(mediatek): update EMI stub implementation 97881aacebc2 feat(mediatek): add APIs exposed to the static library c33b98d7b84d feat(mt8196): add MMinfra support 31a69d9ae79c feat(mt8196): add UFS functions used by the static library 22c454d464cf Merge "docs: remove Chris from LTS maintainers" into integration c17351450c8a Merge "docs(changelog): changelog for v2.13 release" into integration a6f0886076d1 Merge "fix(fvp): increase EventLog size for OP-TEE with multiple SPs" into integration 9c1201887340 docs: remove Chris from LTS maintainers 97a6de9e9b62 docs(changelog): changelog for v2.13 release d1a824ea0e88 fix(fvp): increase EventLog size for OP-TEE with multiple SPs bb9e34f99ca7 feat(intel): update CPUECTLR_EL1 to boost ethernet performance 4c449fcad3c5 feat(mt8189): add IOMMU enable control in SiP service f69f551269f1 feat(smcc): introduce a new vendor_el3 service for ACS SMC handler 9adc42705a63 fix(st-iwdg): remove num_irq adeee68b8a08 fix(st-drivers): remove useless field in fixed regul b43afb7fe16c fix(st-bsec): remove useless defines in BSEC3 6fede181224f fix(st-bsec): rename OTPSR field 6bc7c5b70eba fix(st-crypto): do not set IPRST if BUSY flag is present 6851fd9ecccd fix(st-ddr): bad refresh update level toggle sequence fd5e5e7b7184 fix(st-ddr): remove TODO in STM32MP2 driver f53f260f7b78 fix(stm32mp2): correct typo in definition header 72b9f52d373b feat(versal): add hooks for mmap and early setup 55f6ea4dadb2 refactor(zynqmp): refactor custom sip service 48afc8e5ecee chore(fvp): remove unused macro definition da2c9e58d00c docs(versal-net): update documentation for SDEI Change-Id: I8720c180141549a2c075455174ac475381a35997 Signed-off-by: Yidi Lin <yidilin@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> |
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coreboot README
coreboot is a Free Software project aimed at replacing the proprietary firmware (BIOS/UEFI) found in most computers. coreboot performs the required hardware initialization to configure the system, then passes control to a different executable, referred to in coreboot as the payload. Most often, the primary function of the payload is to boot the operating system (OS).
With the separation of hardware initialization and later boot logic, coreboot is perfect for a wide variety of situations. It can be used for specialized applications that run directly in the firmware, running operating systems from flash, loading custom bootloaders, or implementing firmware standards, like PC BIOS services or UEFI. This flexibility allows coreboot systems to include only the features necessary in the target application, reducing the amount of code and flash space required.
Source code
All source code for coreboot is stored in git. It is downloaded with the command:
git clone https://review.coreboot.org/coreboot.git.
Code reviews are done in the project's Gerrit instance.
The code may be browsed via coreboot's Gitiles instance.
The coreboot project also maintains a mirror of the project on github. This is read-only, as coreboot does not accept github pull requests, but allows browsing and downloading the coreboot source.
Payloads
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://doc.coreboot.org/payloads.html for a list of some of coreboot's supported payloads.
Supported Hardware
The coreboot project supports a wide range of architectures, chipsets, devices, and mainboards. While not all of these are documented, you can find some information in the Architecture-specific documentation or the SOC-specific documentation.
For details about the specific mainboard devices that coreboot supports, please consult the Mainboard-specific documentation or the Board Status pages.
Releases
Releases are currently done by coreboot every quarter. The release archives contain the entire coreboot codebase from the time of the release, along with any external submodules. The submodules containing binaries are separated from the general release archives. All of the packages required to build the coreboot toolchains are also kept at coreboot.org in case the websites change, or those specific packages become unavailable in the future.
All releases are available on the coreboot download page.
Please note that the coreboot releases are best considered as snapshots of the codebase, and do not currently guarantee any sort of extra stability.
Build Requirements and building coreboot
The coreboot build, associated utilities and payloads require many additional tools and packages to build. The actual coreboot binary is typically built using a coreboot-controlled toolchain to provide reproducibility across various platforms. It is also possible, though not recommended, to make it directly with your system toolchain. Operating systems and distributions come with an unknown variety of system tools and utilities installed. Because of this, it isn't reasonable to list all the required packages to do a build, but the documentation lists the requirements for a few different Linux distributions.
To see the list of tools and libraries, along with a list of instructions to get started building coreboot, go to the Starting from scratch tutorial page.
That same page goes through how to use QEMU to boot the build and see the output.
Website and Mailing List
Further details on the project, as well as links to documentation and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://doc.coreboot.org/community/forums.html
Copyrights and Licenses
Uncopyrightable files
There are many files in the coreboot tree that we feel are not copyrightable due to a lack of creative content.
"In order to qualify for copyright protection in the United States, a work must satisfy the originality requirement, which has two parts. The work must have “at least a modicum” of creativity, and it must be the independent creation of its author."
https://guides.lib.umich.edu/copyrightbasics/copyrightability
Similar terms apply to other locations.
These uncopyrightable files include:
- Empty files or files with only a comment explaining their existence. These may be required to exist as part of the build process but are not needed for the particular project.
- Configuration files either in binary or text form. Examples would be files such as .vbt files describing graphics configuration, .apcb files containing configuration parameters for AMD firmware binaries, and spd files as binary .spd or text *spd*.hex representing memory chip configuration.
- Machine-generated files containing version numbers, dates, hash values or other "non-creative" content.
As non-creative content, these files are in the public domain by default. As such, the coreboot project excludes them from the project's general license even though they may be included in a final binary.
If there are questions or concerns about this policy, please get in touch with the coreboot project via the mailing list.
Copyrights
The copyright on coreboot is owned by quite a large number of individual developers and companies. A list of companies and individuals with known copyright claims is present at the top level of the coreboot source tree in the 'AUTHORS' file. Please check the git history of each of the source files for details.
Licenses
Because of the way coreboot began, using a significant amount of source code from the Linux kernel, it's licensed the same way as the Linux Kernel, with GNU General Public License (GPL) Version 2. Individual files are licensed under various licenses, though all are compatible with GPLv2. The resulting coreboot image is licensed under the GPL, version 2. All source files should have an SPDX license identifier at the top for clarification.
Files under coreboot/Documentation/ are licensed under CC-BY 4.0 terms. As an exception, files under Documentation/ with a history older than 2017-05-24 might be under different licenses.
Files in the coreboot/src/commonlib/bsd directory are all licensed with the BSD-3-clause license. Many are also dual-licensed GPL-2.0-only or GPL-2.0-or-later. These files are intended to be shared with libpayload or other BSD licensed projects.
The libpayload project contained in coreboot/payloads/libpayload may be licensed as BSD or GPL, depending on the code pulled in during the build process. All GPL source code should be excluded unless the Kconfig option to include it is set.
The Software Freedom Conservancy
Since 2017, coreboot has been a member of The Software Freedom Conservancy, a nonprofit organization devoted to ethical technology and driving initiatives to make technology more inclusive. The conservancy acts as coreboot's fiscal sponsor and legal advisor.