Felix Held d992aa6111 soc/amd/common/lpc/espi_util: simplify espi_get_general_configuration ... The intermediate ret variable isn't needed. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4e6747cf468c5ba8da6c1a3b20022851e32ad951 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>		2021-12-20 17:39:46 +00:00
..
cezanne	soc/amd/cezanne/fch: disable 48MHz output in S0i3	2021-12-20 17:39:29 +00:00
common	soc/amd/common/lpc/espi_util: simplify espi_get_general_configuration	2021-12-20 17:39:46 +00:00
picasso	soc/amd: remove root of SoC directory from include path	2021-12-20 09:51:49 +00:00
stoneyridge	soc/amd/stoneyridge/fch: add GNVS-related TODOs	2021-12-20 17:38:54 +00:00
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