coreboot/src/soc
Meera Ravindranath d980339aca soc/intel/jasperlake: Fix PMC_GPE_DW mapping
PMC_GPE_DW mapping was not configured correctly and hence
coreboot skipped programming Tier 1 GPIOs resulting in failure of
S3 wake from Trackpad.

TEST=System should wake from S3 via trackpad

Change-Id: I59ce3720e0ffeefb2c9440bb300689def80211ea
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-08-18 13:56:27 +00:00
..
amd src: Remove unused 'include <delay.h>' 2020-08-18 12:19:18 +00:00
cavium src: Remove unused 'include <types.h>' 2020-07-14 16:10:17 +00:00
intel soc/intel/jasperlake: Fix PMC_GPE_DW mapping 2020-08-18 13:56:27 +00:00
mediatek src: Remove unused 'include <delay.h>' 2020-08-18 12:19:18 +00:00
nvidia src: Remove unused 'include <stddef.h> 2020-08-18 12:15:44 +00:00
qualcomm src: Remove unused 'include <delay.h>' 2020-08-18 12:19:18 +00:00
rockchip src/soc/rockchip: Add missing <{stddef,stdint}.h> 2020-07-29 09:37:22 +00:00
samsung src/soc/samsung/exynos{5250,s5420}: Add missing <{stddef,stdint}.h> 2020-07-29 09:34:55 +00:00
sifive treewide: Add Kconfig variable MEMLAYOUT_LD_FILE 2020-06-13 06:49:23 +00:00
ucb soc/ucb/riscv: Add chip_operations stub 2020-05-28 09:30:35 +00:00