Thaminda Edirisooriya d9653e1328 riscv-trap-handling: Add functionality, prevent stack corruption ... Trap handling code was bugged in that it loaded in the wrong stack pointer, overwriting the space the processor uses to talk to its host for doing device requests. Fix this issue, as well as add support for handling misaligned loads the same way we handle misaligned stores. Change-Id: I68ba3a114b7167b3212bb0bed181a7595f0b97d8 Signed-off-by: Thaminda Edirisooriya <thaminda@google.com> Reviewed-on: http://review.coreboot.org/11620 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>		2015-09-15 18:04:37 +00:00
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arm	linking: add and use LDFLAGS_common	2015-09-09 19:35:54 +00:00
arm64	linking: add and use LDFLAGS_common	2015-09-09 19:35:54 +00:00
mips	linking: add and use LDFLAGS_common	2015-09-09 19:35:54 +00:00
riscv	riscv-trap-handling: Add functionality, prevent stack corruption	2015-09-15 18:04:37 +00:00
x86	x86: link ramstage the same way regardless of RELOCATABLE_RAMSTAGE	2015-09-09 19:36:08 +00:00