97dbfd3098
On older CPUs lacking ESRM (Enhanced Short Rep Mov) the rep stos instructions are very slow. Since the MTRR that covers the SPI ROM is disabled when setting up the NEM, the CPU will run with cache disabled and is even slower. The Sandy Bridge BWG and the Sandy Bridge UEFI reference code do not disable the MTRR on the XiP, allowing the CPU to run at full speed when setting up CAR. On UEFI the CAR is set up by touching each cache-line once. It doesn't clear the CAR while doing so. Do the same to speed up setting CAR: - Invalidate the cache - Enable the SPI ROM XiP MTRR - Set CR0.CD=0 - Touch one spot in each cache-line - Clear CAR after NEM has been set up To ensure that the CAR MTRR area is 64-byte aligned add an ALIGN to the linker script. All existing boards should use a 64-byte alignment for CAR. TEST=Booted on Lenovo X220 and measured with cbmem -t: TODO: Test on platforms that have FSRM (Ivy Bridge and newer). Before: 0:1st timestamp 1,083 (0) 11:start of bootblock 93,765 (92,681) After: 0:1st timestamp 0 11:start of bootblock 24,027 Boots 69msec faster than before or about 4 times faster. Change-Id: Ia8baef28fd736ef6bb02d8a100d752ac0392e1cf Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/88792 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> |
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| amd | ||
| armltd | ||
| intel | ||
| power9 | ||
| qemu-power8 | ||
| qemu-x86 | ||
| via | ||
| x86 | ||
| Kconfig | ||
| Makefile.mk | ||