coreboot/src
Arthur Heymans d81078d944 nb/i945/gma.c: Remove writes to FIFO Watermark registers
Those are the result from tracing what linux or the option rom do
but are not needed here.

TESTED on Thinkpad X60.

Change-Id: I4297a78c4ab6a19ef6161778c993fc3f3fb08c7e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18294
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-02-14 13:03:02 +01:00
..
acpi
arch x86/acpi: Add VFCT table 2017-02-04 23:01:37 +01:00
commonlib buildsystem: Drop explicit (k)config.h includes 2016-12-08 19:46:53 +01:00
console console: Enable do_printk_va_list for VBOOT 2016-12-27 18:07:39 +01:00
cpu cpu/intel/model_6fx: Add Conroe-L to cpu_device_id list 2017-01-10 19:54:12 +01:00
device ddr3 spd: move accessor code into lib/spd_bin.c 2017-02-10 18:04:33 +01:00
drivers drivers/intel/gma/vbt: Add Kconfig symbol for SSC ref 2017-02-04 23:04:06 +01:00
ec ec/google/chromeec: let platform prepare for reboot when resetting EC 2017-02-07 17:45:05 +01:00
include ddr3 spd: move accessor code into lib/spd_bin.c 2017-02-10 18:04:33 +01:00
lib ddr3 spd: move accessor code into lib/spd_bin.c 2017-02-10 18:04:33 +01:00
mainboard google/poppy: select NO_FADT_8042 2017-02-14 00:51:30 +01:00
northbridge nb/i945/gma.c: Remove writes to FIFO Watermark registers 2017-02-14 13:03:02 +01:00
soc intel/skylake: Disable FADT.8042 if NO_FADT_8042 is set 2017-02-14 00:51:21 +01:00
southbridge southbridge/intel/common/firmware: allow locking ME without HAVE_ME_BIN 2017-02-08 15:12:50 +01:00
superio sio/ite/it8783ef: Return (0) in ACPI _PSC methods 2016-12-13 22:49:24 +01:00
vboot build system: mark sub-make invocations as parallelizable 2017-01-31 18:51:55 +01:00
vendorcode AGESA: Remove nonexistent include path 2017-02-14 10:57:45 +01:00
Kconfig device/dram: use global DIMM_SPD_SIZE Kconfig variable 2017-02-10 17:57:15 +01:00