Raul E Rangel d75ee46d3c soc/amd/picasso/acpi: Change PCI0 BAR window ... Picasso currently declares the BAR region between TOM and IO_APIC_ADDR. This region includes MMCONF. We don't want to map any PCI BARs in this region. This also matches what intel does. See soc/intel/braswell/acpi/southcluster.asl for an example. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I9474fd6ac75a7245b3c35151c38186e913219bb0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>		2021-02-22 07:29:41 +00:00
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cezanne	soc/amd/cezanne/acpi: Add pci0.asl	2021-02-22 07:29:31 +00:00
common	soc/amd: Move root complex SSDT TOM1/TOM2 generation function	2021-02-22 07:29:19 +00:00
picasso	soc/amd/picasso/acpi: Change PCI0 BAR window	2021-02-22 07:29:41 +00:00
stoneyridge	ACPI: Use common OperationRegion for PCI_MMCONF	2021-02-20 21:38:54 +00:00
Kconfig