Lee Leahy d75ed0bfd9 soc/intel/quark: Disable the ROM shadow ... Disable the ROM shadow and enable RAM for 0x000e0000 - 0x000fffff. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Testing successful display of 0x000ffff0 - 0x000fffff does not match the end of the SPI flash. Change-Id: I6e0a50417815320333eae0b69b96280c39db7eaa Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14110 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>		2016-03-21 19:46:59 +01:00
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apollolake	soc/intel/apollolake: Avoid hardcoding CAR region size for FSPM	2016-03-11 16:55:51 +01:00
baytrail	x86 chipsets: utilize x86_setup_mtrrs_with_detect()	2016-03-08 23:58:01 +01:00
braswell	x86 chipsets: utilize x86_setup_mtrrs_with_detect()	2016-03-08 23:58:01 +01:00
broadwell	x86 chipsets: utilize x86_setup_mtrrs_with_detect()	2016-03-08 23:58:01 +01:00
common	soc/intel/common: Use SoC specific routine to read/write MTRRs	2016-02-02 19:00:35 +01:00
fsp_baytrail	intel/fsp_baytrail: Enable LPSS in ACPI mode	2016-03-14 18:24:10 +01:00
quark	soc/intel/quark: Disable the ROM shadow	2016-03-21 19:46:59 +01:00
skylake	intel/skylake: Do not log wake source on reset	2016-03-12 09:23:15 +01:00