aa3cfd5c69
Once the MPLL has been initialised, convert the timings from the SPD to be in DCLKs, which is what the hardware expects. In addition, calculate the values for tREFI and tXP. Change-Id: Id02caf858f75b9e08016762b3aefda282b274386 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> |
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