7f8afe0631
Certain chipsets don't have a memory-mapped boot media so their code execution for stages prior to DRAM initialization is backed by SRAM or cache-as-ram. The postcar stage/phase handles the cache-as-ram situation where in order to tear down cache-as-ram one needs to be executing out of a backing store that isn't transient. By current definition, cache-as-ram is volatile and tearing it down leads to its contents disappearing. Therefore provide a shim layer, postcar, that's loaded into memory and executed which does 2 things: 1. Tears down cache-as-ram with a chipset helper function. 2. Loads and runs ramstage. Because those 2 things are executed out of ram there's no issue of the code's backing store while executing the code that tears down cache-as-ram. The current implementation makes no assumption regarding cacheability of the DRAM itself. If the chipset code wishes to cache DRAM for loading of the postcar stage/phase then it's also up to the chipset to handle any coherency issues pertaining to cache-as-ram destruction. Change-Id: Ia58efdadd0b48f20cfe7de2f49ab462306c3a19b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14140 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
223 lines
4.9 KiB
C
223 lines
4.9 KiB
C
/*
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* This file is part of the coreboot project.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _RULES_H
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#define _RULES_H
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/* Useful helpers to tell whether the code is executing in bootblock,
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* romstage, ramstage or SMM.
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*/
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#if defined(__BOOTBLOCK__)
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#define ENV_BOOTBLOCK 1
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#define ENV_ROMSTAGE 0
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#define ENV_RAMSTAGE 0
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#define ENV_SMM 0
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#define ENV_VERSTAGE 0
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#define ENV_RMODULE 0
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#define ENV_POSTCAR 0
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#define ENV_STRING "bootblock"
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#elif defined(__ROMSTAGE__)
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#define ENV_BOOTBLOCK 0
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#define ENV_ROMSTAGE 1
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#define ENV_RAMSTAGE 0
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#define ENV_SMM 0
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#define ENV_VERSTAGE 0
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#define ENV_RMODULE 0
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#define ENV_POSTCAR 0
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#define ENV_STRING "romstage"
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#elif defined(__SMM__)
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#define ENV_BOOTBLOCK 0
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#define ENV_ROMSTAGE 0
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#define ENV_RAMSTAGE 0
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#define ENV_SMM 1
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#define ENV_VERSTAGE 0
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#define ENV_RMODULE 0
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#define ENV_POSTCAR 0
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#define ENV_STRING "smm"
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#elif defined(__VERSTAGE__)
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#define ENV_BOOTBLOCK 0
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#define ENV_ROMSTAGE 0
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#define ENV_RAMSTAGE 0
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#define ENV_SMM 0
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#define ENV_VERSTAGE 1
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#define ENV_RMODULE 0
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#define ENV_POSTCAR 0
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#define ENV_STRING "verstage"
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#elif defined(__RAMSTAGE__)
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#define ENV_BOOTBLOCK 0
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#define ENV_ROMSTAGE 0
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#define ENV_RAMSTAGE 1
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#define ENV_SMM 0
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#define ENV_VERSTAGE 0
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#define ENV_RMODULE 0
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#define ENV_POSTCAR 0
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#define ENV_STRING "ramstage"
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#elif defined(__RMODULE__)
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#define ENV_BOOTBLOCK 0
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#define ENV_ROMSTAGE 0
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#define ENV_RAMSTAGE 0
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#define ENV_SMM 0
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#define ENV_VERSTAGE 0
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#define ENV_RMODULE 1
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#define ENV_POSTCAR 0
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#define ENV_STRING "rmodule"
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#elif defined(__POSTCAR__)
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#define ENV_BOOTBLOCK 0
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#define ENV_ROMSTAGE 0
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#define ENV_RAMSTAGE 0
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#define ENV_SMM 0
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#define ENV_VERSTAGE 0
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#define ENV_RMODULE 0
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#define ENV_POSTCAR 1
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#define ENV_STRING "postcar"
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#else
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/*
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* Default case of nothing set for random blob generation using
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* create_class_compiler that isn't bound to a stage. Also AGESA
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* apparently builds things compeletely separate from coreboot's
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* build infrastructure -- hardcoding its own rules.
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*/
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#define ENV_BOOTBLOCK 0
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#define ENV_ROMSTAGE 0
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#define ENV_RAMSTAGE 0
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#define ENV_SMM 0
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#define ENV_VERSTAGE 0
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#define ENV_RMODULE 0
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#define ENV_POSTCAR 0
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#define ENV_STRING "UNKNOWN"
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#endif
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/* For pre-DRAM stages and post-CAR always build with simple device model, ie.
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* PCI, PNP and CPU functions operate without use of devicetree. The reason
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* post-CAR utilizes __SIMPLE_DEVICE__ is for simplicity. Currently there's
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* no known requirement that devicetree would be needed during that stage.
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*
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* For ramstage individual source file may define __SIMPLE_DEVICE__
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* before including any header files to force that particular source
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* be built with simple device model.
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*/
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#if defined(__PRE_RAM__) || ENV_SMM || ENV_POSTCAR
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#define __SIMPLE_DEVICE__
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#endif
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/* Define helpers about the current architecture, based on toolchain.inc. */
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#if defined(__ARCH_arm__)
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#define ENV_ARM 1
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#define ENV_ARM64 0
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#if __COREBOOT_ARM_ARCH__ == 4
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#define ENV_ARMV4 1
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#define ENV_ARMV7 0
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#elif __COREBOOT_ARM_ARCH__ == 7
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#define ENV_ARMV4 0
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#define ENV_ARMV7 1
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#else
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#define ENV_ARMV4 0
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#define ENV_ARMV7 0
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#endif
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#define ENV_ARMV8 0
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#define ENV_MIPS 0
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#define ENV_RISCV 0
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#define ENV_X86 0
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#define ENV_X86_32 0
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#define ENV_X86_64 0
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#elif defined(__ARCH_arm64__)
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#define ENV_ARM 0
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#define ENV_ARM64 1
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#define ENV_ARMV4 0
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#define ENV_ARMV7 0
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#if __COREBOOT_ARM_ARCH__ == 8
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#define ENV_ARMV8 1
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#else
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#define ENV_ARMV8 0
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#endif
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#define ENV_MIPS 0
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#define ENV_RISCV 0
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#define ENV_X86 0
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#define ENV_X86_32 0
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#define ENV_X86_64 0
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#elif defined(__ARCH_mips__)
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#define ENV_ARM 0
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#define ENV_ARM64 0
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#define ENV_ARMV4 0
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#define ENV_ARMV7 0
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#define ENV_ARMV8 0
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#define ENV_MIPS 1
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#define ENV_RISCV 0
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#define ENV_X86 0
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#define ENV_X86_32 0
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#define ENV_X86_64 0
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#elif defined(__ARCH_riscv__)
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#define ENV_ARM 0
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#define ENV_ARM64 0
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#define ENV_ARMV4 0
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#define ENV_ARMV7 0
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#define ENV_ARMV8 0
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#define ENV_MIPS 0
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#define ENV_RISCV 1
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#define ENV_X86 0
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#define ENV_X86_32 0
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#define ENV_X86_64 0
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#elif defined(__ARCH_x86_32__)
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#define ENV_ARM 0
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#define ENV_ARM64 0
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#define ENV_ARMV4 0
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#define ENV_ARMV7 0
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#define ENV_ARMV8 0
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#define ENV_MIPS 0
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#define ENV_RISCV 0
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#define ENV_X86 1
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#define ENV_X86_32 1
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#define ENV_X86_64 0
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#elif defined(__ARCH_x86_64__)
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#define ENV_ARM 0
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#define ENV_ARM64 0
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#define ENV_ARMV4 0
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#define ENV_ARMV7 0
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#define ENV_ARMV8 0
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#define ENV_MIPS 0
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#define ENV_RISCV 0
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#define ENV_X86 1
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#define ENV_X86_32 0
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#define ENV_X86_64 1
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#else
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#define ENV_ARM 0
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#define ENV_ARM64 0
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#define ENV_ARMV4 0
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#define ENV_ARMV7 0
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#define ENV_ARMV8 0
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#define ENV_MIPS 0
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#define ENV_RISCV 0
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#define ENV_X86 0
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#define ENV_X86_32 0
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#define ENV_X86_64 0
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#endif
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#endif /* _RULES_H */
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