Wim Vervoorn d6b682cf92 soc/intel/skylake: Allow setting of PcieRpMaxPayload ... Add setting of the MaxPayload for each root port from the device tree. By default MaxPayload is set to 128 bytes. This change allows changing to 256 bytes. BUG=N/A TEST=tested on facebook monolith Change-Id: I61e1d619588a7084d52bbe101acd757cc7293cac Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>		2020-05-11 09:30:04 +00:00
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amd	soc/amd/common/block/lpc: Use standard pci_dev_ops_pci	2020-05-07 01:26:23 +00:00
cavium	src/: Replace GPL boilerplate with SPDX headers	2020-05-09 21:22:25 +00:00
intel	soc/intel/skylake: Allow setting of PcieRpMaxPayload	2020-05-11 09:30:04 +00:00
mediatek	src/: Replace GPL boilerplate with SPDX headers	2020-05-09 21:22:25 +00:00
nvidia	src/: Replace GPL boilerplate with SPDX headers	2020-05-09 21:22:25 +00:00
qualcomm	src/: Replace GPL boilerplate with SPDX headers	2020-05-09 21:22:25 +00:00
rockchip	src/: Replace GPL boilerplate with SPDX headers	2020-05-09 21:22:25 +00:00
samsung	treewide: replace GPLv2 long form headers with SPDX header	2020-05-06 22:20:57 +00:00
sifive	soc/sifive/fu540: Add missing '#include <commonlib/bsd/helpers.h>'	2020-05-11 09:25:57 +00:00
ucb	soc/ucb: Use SPDX for GPL-2.0-only files	2020-04-05 17:47:49 +00:00