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Lee Leahy d6b5fb06a5 Broadwell FSP: Add new finalize functions for devices and chips
Merge change from coreboot.org: Add new finalize functions for devices
and chips

BUG=None
TEST=Requires FSP for testing

    commit 2a58ecde78
    Author: Marc Jones <marc.jones@se-eng.com>
    Date:   Tue Oct 29 17:32:00 2013 -0600

    Add new finalize functions for devices and chips

    Many chipset devices require additional configuration after
    device init. It is not uncommmon for a device early in the
    devicetree list to need to change a setting after a device later
    in the tree does PCI init. A final function call has been added
    to device ops to handle this case. It is called prior to coreboot
    table setup.

    Another problem that is often seen is that the chipset or
    mainboard need to do some final cleanup just before loading the
    OS. The chip finalize has been added for this case. It is call
    after all coreboot tables are setup and the payload is ready to
    be called.

    Similar functionality could be implemented with the hardwaremain
    states, but those don't fit well in the device tree function
    pointer structure and should be used sparingly.

    Change-Id: Ib37cce104ae41ec225a8502942d85e54d99ea75f
    Reviewed-on: http://review.coreboot.org/4012
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

Change-Id: I4f918a5908f2016f6e57f954284f9f8856bd8301
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/213694
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/229572
Reviewed-by: Erik C Bjorge <erik.c.bjorge@intel.com>
2014-11-20 20:49:36 +00:00
configs ryu: Add support for event log 2014-11-13 23:27:52 +00:00
documentation documentation: Add documentation for timestamp library 2014-11-14 23:57:04 +00:00
payloads libpayload: arm64: don't modify cbtable entries 2014-11-18 21:11:52 +00:00
src Broadwell FSP: Add new finalize functions for devices and chips 2014-11-20 20:49:36 +00:00
util cbfstool: Add missing break statement 2014-11-18 01:05:55 +00:00
.gitignore rmodules: add support for rmodtool 2014-03-31 22:25:57 +00:00
COMMIT-QUEUE.ini COMMIT-QUEUE.ini: Add documentation. 2013-11-01 14:08:42 +00:00
COPYING update license template. 2006-08-12 22:03:36 +00:00
Makefile Makefile: Change $(generic-deps) to order-only prerequisite 2014-10-04 03:10:51 +00:00
Makefile.inc UPSTREAM:Add Kconfig options for Linux as payload 2014-10-29 22:24:00 +00:00
PRESUBMIT.cfg chromeos: Add PRESUBMIT.cfg 2013-05-01 14:31:10 -07:00
README Update README with newer version of the text from the web page 2011-06-15 10:16:33 +02:00
toolchain.inc arch/mips: Add base MIPS architecture support 2014-09-01 11:05:57 +00:00

-------------------------------------------------------------------------------
coreboot README
-------------------------------------------------------------------------------

coreboot is a Free Software project aimed at replacing the proprietary BIOS
(firmware) found in most computers.  coreboot performs a little bit of
hardware initialization and then executes additional boot logic, called a
payload.

With the separation of hardware initialization and later boot logic,
coreboot can scale from specialized applications that run directly
firmware, run operating systems in flash, load custom
bootloaders, or implement firmware standards, like PC BIOS services or
UEFI. This allows for systems to only include the features necessary
in the target application, reducing the amount of code and flash space
required.

coreboot was formerly known as LinuxBIOS.


Payloads
--------

After the basic initialization of the hardware has been performed, any
desired "payload" can be started by coreboot.

See http://www.coreboot.org/Payloads for a list of supported payloads.


Supported Hardware
------------------

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

 * http://www.coreboot.org/Supported_Motherboards
 * http://www.coreboot.org/Supported_Chipsets_and_Devices


Build Requirements
------------------

 * gcc / g++
 * make

Optional:

 * doxygen (for generating/viewing documentation)
 * iasl (for targets with ACPI support)
 * gdb (for better debugging facilities on some targets)
 * ncurses (for 'make menuconfig')
 * flex and bison (for regenerating parsers)


Building coreboot
-----------------

Please consult http://www.coreboot.org/Build_HOWTO for details.


Testing coreboot Without Modifying Your Hardware
------------------------------------------------

If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run
coreboot virtually in QEMU.

Please see http://www.coreboot.org/QEMU for details.


Website and Mailing List
------------------------

Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the coreboot website:

  http://www.coreboot.org

You can contact us directly on the coreboot mailing list:

  http://www.coreboot.org/Mailinglist


Copyright and License
---------------------

The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files are licensed under the "GPL, version 2". For some parts, which
were derived from other projects, other (GPL-compatible) licenses may apply.
Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.