coreboot/superio/fintek/f71805f/dts
Stefan Reinauer 6220b632e7 Now version 3: LinuxBIOS -> coreboot rename.
- I left LB_TAG_ intact because they are used by the payloads
- file renames are still missing. see next commit
- some lb_ renames might be missing. feel free to provide patches.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@564 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-01-27 18:54:57 +00:00

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
{
/* Floppy */
floppydev = "0x0";
floppyenable = "0";
floppyio = "0x3f0";
floppyirq = "6";
floppydrq = "2";
/* Parallel port */
ppdev = "1";
ppenable = "1";
ppio = "0x378";
ppirq = "7";
/* Note: renaming from comx to spx may have broken the DTS
* We'll find out later */
/* Serial Port 1 */
sp1dev = "2";
sp1enable = "1";
sp1io = "0x3f8";
sp1irq = "4";
/* Serial Port 2 */
sp2dev = "3";
sp2enable = "1";
sp2io = "0x2f8";
sp2irq = "3";
/* Hardware Monitor */
hwmdev = "0xb";
hwmenable = "0";
hwmio = "0xec00";
};