04f83ff7dc
AMD systems have a TOM2WB bit in SYS_CFG MSR to forcefully cover the address space between 4GB-TOM2 as WB. Any WB MTRR that falls into that range may be skipped from programming. It can save a lot of MTRRs when calculating the MTRR solution. It is especially needed when using a temporary MTRR to cover the flash as WP, as the MTRR space gets more fragmented. Add checks for SYS_CFG TOM2WB in the MTRR driver and skip the WB MTRR ranges when possible. TEST=Successfully enable temporary MTRR range for flash on Gigabyte MZ33-AR1. Change-Id: Ie9af9b54a1037c843d8f019506af761a8d8769d0 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/89199 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> |
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| intel | ||
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| x86 | ||
| Kconfig | ||
| Makefile.mk | ||