coreboot/src/soc
Lee Leahy d52636113a soc/intel/quark: Disable FSP serial output
Disable FSP output when CONFIG_DEFAULT_CONSOLE_LOGLEVEL is not set to 8
(BIOS_SPEW).  Use the console log level to choose between the serial
port address and NULL and pass it to FSP for the serial port address.

TEST=Build and run on Galileo Gen2.

Change-Id: I5498aad218524c211082d85d0ae9aacaf08a80f6
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16005
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-05 01:54:55 +02:00
..
broadcom/cygnus Remove non-ascii & unprintable characters 2016-08-01 21:44:45 +02:00
dmp/vortex86ex src/soc: Capitalize CPU, ACPI, RAM and ROM 2016-07-31 19:27:53 +02:00
imgtec/pistachio drivers/uart: Use uart_platform_refclk for all UART models 2016-05-09 18:45:44 +02:00
intel soc/intel/quark: Disable FSP serial output 2016-08-05 01:54:55 +02:00
marvell src/soc: Capitalize CPU, ACPI, RAM and ROM 2016-07-31 19:27:53 +02:00
mediatek/mt8173 Remove extra newlines from the end of all coreboot files. 2016-07-31 18:19:33 +02:00
nvidia src/soc: Capitalize CPU, ACPI, RAM and ROM 2016-07-31 19:27:53 +02:00
qualcomm google/gale: Add more board ID variants 2016-08-03 18:23:47 +02:00
rdc/r8610 rdc/r8610: Move to src/soc 2016-05-05 20:08:58 +02:00
rockchip google/gru: Add code to support I2C TPM for Kevin 2016-08-03 18:23:23 +02:00
samsung src/soc: Capitalize CPU, ACPI, RAM and ROM 2016-07-31 19:27:53 +02:00
ucb/riscv arch/riscv: Move CBMEM into RAM 2016-07-15 03:01:02 +02:00