coreboot/src
Aaron Durbin 99d8818af3 baytrail: don't allow PCIE wake ups
The PCIe subsystem was constantly waking up boards from
S3 and S5. Completely disable PCIe wake ups. It can be made
mainboard-configurable later if needed.

BUG=chrome-os-partner:24004
BRANCH=None
TEST=Both S3 and EC RW->RW update (trip through S5) don't
     cause wakeups.

Change-Id: I922e2947c4b6e29277d913f06192601a2954f8fe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176791
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4972
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07 12:05:58 +02:00
..
arch Introduce stage-specific architecture for coreboot 2014-05-06 20:23:31 +02:00
console console: Fix UART selection prompt 2014-04-30 23:47:28 +02:00
cpu Introduce stage-specific architecture for coreboot 2014-05-06 20:23:31 +02:00
device Introduce stage-specific architecture for coreboot 2014-05-06 20:23:31 +02:00
drivers drivers/pc80/Kconfig: Do not init PS/2 keyboard if GRUB 2 is chosen as payload 2014-05-02 15:05:07 +02:00
ec Declare recovery and developer modes outside ChromeOS 2014-05-01 15:38:41 +02:00
include Introduce stage-specific architecture for coreboot 2014-05-06 20:23:31 +02:00
lib reg_script: add iosf lpss port access 2014-05-07 12:05:01 +02:00
mainboard rambi: fixup settings so trackpad can be found in kernel 2014-05-07 12:05:19 +02:00
northbridge northbridge/intel/sandybridge/pei_data.h: Fix typo in hig*h*est in comment 2014-05-06 13:55:39 +02:00
soc baytrail: don't allow PCIE wake ups 2014-05-07 12:05:58 +02:00
southbridge AGESA SPI: Fix Kconfig options 2014-04-29 17:31:40 +02:00
superio Introduce stage-specific architecture for coreboot 2014-05-06 20:23:31 +02:00
vendorcode Introduce stage-specific architecture for coreboot 2014-05-06 20:23:31 +02:00
Kconfig Introduce stage-specific architecture for coreboot 2014-05-06 20:23:31 +02:00