coreboot/src/soc/intel
Lee Leahy d4edacb2e4 soc/intel/quark: Call FSP SiliconInit
Optionally relocate FSP into DRAM and then call FSP SiliconInit.

Testing on Galileo:
*  Edit the src/mainboard/intel/galileo/Makefile.inc file
   *  Add "select ADD_FSP_PDAT_FILE"
   *  Add "select ADD_FSP_RAW_BIN"
   *  Add "select ADD_RMU_FILE"
   *  Add "select DISPLAY_FSP_ENTRY_POINTS"
   *  Add "select DISPLAY_HOBS"
   *  Optionally add "select RELOCATE_FSP_INTO_DRAM"
*  Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
*  Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
*  Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
*  Testing is successful if:
   *  FSP entry points are displayed and
   *  The message "FspSiliconInit returned 0x00000000" is displayed and
   *  The HOBs are displayed correctly and
   *  The message "ERROR - Missing one or more required FSP HOBs!" is
not displayed

Change-Id: I91e660ea373a8bb00fc97fe8b760347cbfa96b1e
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13631
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-10 03:12:10 +01:00
..
apollolake soc/intel: Add skeleton infrastructure for Apollolake SOC 2016-01-30 03:12:16 +01:00
baytrail ACPI: Fix IASL Warning about unused method for GBUF check 2015-12-10 16:30:50 +01:00
braswell drivers/intel/fsp1_1: Fix spelling error in API and copyright 2016-01-31 20:51:29 +01:00
broadwell chromeos: Remove CONFIG_VBNV_SIZE variable 2016-02-09 13:19:48 +01:00
common soc/intel/common: Use SoC specific routine to read/write MTRRs 2016-02-02 19:00:35 +01:00
fsp_baytrail soc/fsp_baytrail: Add support for FSP MR 005 2016-02-10 02:45:56 +01:00
quark soc/intel/quark: Call FSP SiliconInit 2016-02-10 03:12:10 +01:00
skylake intel/skylake: Add gpio macro for unused GPIO pins 2016-02-09 19:44:57 +01:00