coreboot/src
Arthur Heymans d4e5762bd7 nb/intel/x4x: Fix computing page_size
This variable needs to be in byte so a division by 8 needs to happen.

This problem was introduced by 3cf94032b "nb/x4x/raminit: Rewrite SPD
decode and timing selection", but was probably not encountered because
such dimms are rather uncommon.

Change-Id: I2d57f5e584ac7fa1479791c239432005fe8c178d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22991
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-28 15:42:47 +00:00
..
acpi
arch RISC-V boards: Remove PAGETABLES section from memlayout.ld 2018-04-27 09:07:43 +00:00
commonlib compiler.h: add __weak macro 2018-04-24 14:37:59 +00:00
console src/console: Add spaces around '==' 2018-04-28 15:22:12 +00:00
cpu arch/x86: Fix call for wait_other_cpus_stop() 2018-04-28 14:55:25 +00:00
device device: Add flag to disable PCIe ASPM 2018-04-26 21:32:48 +00:00
drivers drivers/usb: Add spaces around '==' 2018-04-27 17:48:58 +00:00
ec compiler.h: add __weak macro 2018-04-24 14:37:59 +00:00
include device: Add flag to disable PCIe ASPM 2018-04-26 21:32:48 +00:00
lib lib/ext_stage_cache: include prog arg in stage cache metadata 2018-04-24 14:39:36 +00:00
mainboard mainboard/asus: Add spaces around '==' 2018-04-28 15:20:24 +00:00
northbridge nb/intel/x4x: Fix computing page_size 2018-04-28 15:42:47 +00:00
security security/vboot: Add function to check if UDC can be enabled 2018-04-27 02:51:32 +00:00
soc soc/intel/apollolake: enable cache-as-ram paging for glk 2018-04-27 18:48:10 +00:00
southbridge src/southbridge/sis/sis966/nic.c: Improve code formatting 2018-04-28 15:40:53 +00:00
superio
vendorcode vendorcode/intel: Update GLK FSP Header files w.r.t FSP v2.0.2 2018-04-27 03:25:43 +00:00
Kconfig Timestamps: Add option to print timestamps to debug console 2018-03-09 17:16:21 +00:00