Philipp Hug d4ab5bbc82 src/arch/riscv/misaligned.c: Fix an off-by-one error when loading the opcode ... Pointer to opcode increases by unit uint16_t not byte. Change-Id: I2986ca5402ad86d80e0eb955478bfbdc5d50e1f5 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/29339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>		2018-10-30 02:07:58 +00:00
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arm	selfboot: remove bounce buffers	2018-10-11 17:42:41 +00:00
arm64	selfboot: create selfboot_check function, remove check param	2018-10-25 16:57:51 +00:00
mips	selfboot: remove bounce buffers	2018-10-11 17:42:41 +00:00
power8	selfboot: remove bounce buffers	2018-10-11 17:42:41 +00:00
riscv	src/arch/riscv/misaligned.c: Fix an off-by-one error when loading the opcode	2018-10-30 02:07:58 +00:00
x86	arch/x86/acpi: Add TPM2 table support	2018-10-26 11:22:58 +00:00