Felix Held d40e8b6cb5 soc/amd/sabrina: change MAX_CPUS to 8 ... The Sabrina APU has a maximum configuration of 4 physical cores with 2 threads each, so a total of 8 CPU cores. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I627ed78ffba6098726c9c8ec55b60665503240ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/65068 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2022-06-10 17:06:27 +00:00
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acpi	ec/google/chromeec: Add retimer handle to Type C conn	2022-05-04 13:15:30 +00:00
arch	arch/x86/acpi: Replace ShiftLeft() with ASL 2.0 syntax	2022-06-09 09:07:18 +00:00
commonlib	commonlib: Clean up compiler.h	2022-06-07 12:34:35 +00:00
console
cpu	arch/x86: Add a common romstage entry	2022-06-07 12:54:39 +00:00
device	dev/i2c_bus: Add declaration, implementation of i2c_dev_detect()	2022-05-31 13:43:39 +00:00
drivers	drivers/intel/gma/acpi: Replace LNotEqual(a,b) with ASL 2.0 syntax	2022-06-09 08:57:33 +00:00
ec	ec/google/chromeec: Add support to report fan speed via ACPI	2022-06-10 13:12:45 +00:00
include	soc/amd/sabrina/acpi: Correct VID decoding on Sabrina	2022-06-09 18:06:05 +00:00
lib	Replace some ENV_ROMSTAGE with ENV_RAMINIT	2022-06-07 12:53:19 +00:00
mainboard	mb/chausie/ec: Set MS bit in SW02	2022-06-10 15:21:57 +00:00
northbridge	drivers/amd/agesa: Don't save regular boot MTRR to flash	2022-06-06 08:57:09 +00:00
security	drivers/tpm/cr50: Add TPM IRQ timeout Kconfig option	2022-06-08 00:28:27 +00:00
soc	soc/amd/sabrina: change MAX_CPUS to 8	2022-06-10 17:06:27 +00:00
southbridge	Replace some ENV_ROMSTAGE with ENV_RAMINIT	2022-06-07 12:53:19 +00:00
superio	superio/winbond/w83667hg-a: Replace LEqual(a,b) with ASL 2.0 syntax	2022-06-09 09:05:56 +00:00
vendorcode	vc/intel/fsp/fsp2_0/mtl: Add FSP header files (2173_00) for Meteor Lake	2022-06-09 13:49:53 +00:00
Kconfig	src/Kconfig: Fix a spelling issue	2022-05-30 04:25:20 +00:00