Duncan Laurie 5d5de24783 falco: Update DIMM SPD table ... RAM_ID indices have been changed and settled on a 2GB config that will be the same DRAM chips but only used in one channel. BUG=chrome-os-partner:19657 BRANCH=none TEST=emerge-falco chromeos-coreboot-falco Change-Id: I444e655883ae045622ab3dfb964da4d7f86e1c0d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56810 Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2013-05-28 10:38:49 -07:00
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arch	smbios: Add generic type41 write function	2013-05-24 14:02:57 -07:00
console	console: Make use of CONFIG_USE_OPTION_TABLE	2013-04-01 20:54:48 +02:00
cpu	exynos5420: Replace the 5250 clock logic with 5420.	2013-05-22 04:53:51 -07:00
device	device tree: track init times	2013-05-01 15:36:25 -07:00
drivers	elog: Check for successful flash erase in elog_shrink	2013-05-24 14:02:57 -07:00
ec	ec: Remove hardcoded GPI offset in EC SCI	2013-05-21 11:18:56 -07:00
include	smbios: Add generic type41 write function	2013-05-24 14:02:57 -07:00
lib	BACKPORT: cbmem console: use cache-as-ram API and cleanup	2013-05-16 15:06:26 -07:00
mainboard	falco: Update DIMM SPD table	2013-05-28 10:38:49 -07:00
northbridge	haswell: Add magic to turn on grahpics in normal mode	2013-05-28 10:38:48 -07:00
southbridge	lynxpoint: Add ACPI Method to enable GPIO as wake source	2013-05-24 16:27:43 -07:00
superio	Drop prototype guarding for romcc	2013-05-10 11:55:20 -07:00
vendorcode	BACKPORT: chromeos: use cache-as-ram migration API for vbnv	2013-05-16 15:06:25 -07:00
Kconfig	BACKPORT: x86: add thread support	2013-05-15 11:19:50 -07:00