coreboot/src/mainboard/intel
Arthur Heymans d28d507190 sb/intel/bd82x6x/lpc: Set up default LPC decode ranges
This sets up some common default LPC decode ranges in a common place.
This may set up more decode ranges than needed but that typically does
not hurt. Mainboards needing additional ranges can do so in the
mainboard pch_enable_lpc hook.

Change-Id: Ifeb5a862e56f415aa847d0118a33a31537ab8037
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-16 14:08:29 +00:00
..
apollolake_rvp
baskingridge src/mainboard: Remove unused include <device/pci_ops.h> 2019-09-16 07:29:18 +00:00
bayleybay_fsp src/mainboard: Remove unused include <device/pci_ops.h> 2019-09-16 07:29:18 +00:00
camelbackmountain_fsp src/mainboard: Remove unused include <device/pci_ops.h> 2019-09-16 07:29:18 +00:00
cannonlake_rvp mb/*/chromeos.c: Remove some ENV_RAMSTAGE and __SIMPLE_DEVICE__ 2019-07-25 16:03:37 +00:00
coffeelake_rvp mb/*/chromeos.c: Remove some ENV_RAMSTAGE and __SIMPLE_DEVICE__ 2019-07-25 16:03:37 +00:00
d510mo src/mainboard: Remove unused include <device/pci_ops.h> 2019-09-16 07:29:18 +00:00
d945gclf sb/intel/i82801gx: Move CIR init to a common place 2019-10-11 12:21:25 +00:00
dcp847ske sb/intel/bd82x6x/lpc: Set up default LPC decode ranges 2019-10-16 14:08:29 +00:00
dg41wv sb/intel/i82801gx: Move CIR init to a common place 2019-10-11 12:21:25 +00:00
dg43gt soc/intel: Use common romstage code 2019-08-26 21:08:41 +00:00
emeraldlake2 sb/intel/bd82x6x/lpc: Set up default LPC decode ranges 2019-10-16 14:08:29 +00:00
galileo mb/intel/{galileo,wtm2}: Use macro instead of magic number 2019-10-04 16:26:38 +00:00
glkrvp mb/[google/intel]/*: Specify Chrome EC bus - LPC or ESPI 2019-10-03 15:29:53 +00:00
harcuvar src/mainboard: Remove unused include <arch/byteorder.h> 2019-06-19 12:29:18 +00:00
icelake_rvp Split MAYBE_STATIC to _BSS and _NONZERO variants 2019-08-26 20:56:29 +00:00
kblrvp soc/intel/skylake: devicetree: introduce PchHdaVcType fsp parameter 2019-10-02 11:15:00 +00:00
kunimitsu mb/[google/intel/lenovo]/*: fix posix shell bug with SPD files 2019-10-09 22:16:40 +00:00
leafhill
littleplains
minnow3
minnowmax intel/fsp_baytrail: Move TSC_MONOTONIC_TIMER 2019-07-08 09:46:21 +00:00
mohonpeak
saddlebrook mb/{asrock,intel,purism}: Copy channel arrays separately 2019-08-20 15:18:10 +00:00
strago mb/[google/intel]/*: Specify Chrome EC bus - LPC or ESPI 2019-10-03 15:29:53 +00:00
wtm2 mb/intel/{galileo,wtm2}: Use macro instead of magic number 2019-10-04 16:26:38 +00:00
Kconfig
Kconfig.name