coreboot/src/soc
Marshall Dawson d1aa8eba72 amd/stoneyridge: Rename GppClkCntrl fields
Make the field names of the MISCx00 GPPClkCntrl more manageable by
shortening their names.  Make the definitions look more like the
rest of the header file.

Change-Id: I515cd664808e38851a7dbdba899df4fb9bbbcde6
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/29014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-12 15:16:23 +00:00
..
amd amd/stoneyridge: Rename GppClkCntrl fields 2018-10-12 15:16:23 +00:00
broadcom soc/broadcom/cygnus: Increase romstage SRAM size in memlayout 2018-08-13 12:16:32 +00:00
cavium soc/cavium: dynamic UART initialization for cavium cn8100 2018-10-10 16:37:38 +00:00
imgtec src: Use tabs for indentation 2018-10-08 09:46:16 +00:00
intel src: Move common IA-32 MSRs to <cpu/x86/msr.h> 2018-10-11 21:06:53 +00:00
lowrisc/lowrisc mb/lowrisc: Remove the Nexys4DDR port 2018-09-26 15:36:40 +00:00
mediatek mediatek/mt8183: Init PLLs for DRAM 2018-10-10 12:16:43 +00:00
nvidia tegra124_lp0: make sure to build with compiler.h included 2018-10-11 11:00:49 +00:00
qualcomm Move compiler.h to commonlib 2018-10-08 16:57:27 +00:00
rockchip drivers/i2c: Add i2c TPM support for different stages 2018-08-10 23:25:52 +00:00
samsung Move compiler.h to commonlib 2018-10-08 16:57:27 +00:00
sifive soc/sifive/fu540: Document #if ENV_ROMSTAGE line 2018-09-26 18:52:54 +00:00
ucb arch/riscv: provide a monotonic timer 2018-09-14 09:28:06 +00:00