5d291de601
Quoting Wikipedia: A sense amplifier is a circuit that is used to amplify and detect small signals in electronic systems. It is commonly used in memory circuits, such as dynamic random access memory (DRAM), to read and amplify the weak signals stored in memory cells. In this case, we're calibrating the sense amplifiers in the memory controller. This training procedure uses a magic "sense amp offset cancel" mode of the DDRIO to observe the sampled logic levels, and sweeps Vref to find the low-high transition for each bit lane. The procedure consists of two stages: the first stage centers per-byte Vref (to ensure per-bit Vref offsets are as small as possible) and the second stage centers per-bit Vref. Because this procedure uses the "sense amp offset cancel" mode, it does not rely on DRAM being trained. It is assumed that the memory controller simply makes sense amp output levels observable via the `DDR_DATA_TRAIN_FEEDBACK` register and that the memory bus is idle during this training step (so the lane voltage is Vdd / 2). Note: This procedure will need to be adapted for Broadwell because it has per-rank per-bit RxVref registers, whereas Haswell only has a single per-bit RxVref register for all ranks. Change-Id: Ia07db68763f90e9701c8a376e01279ada8dbbe07 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81948 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> |
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