coreboot/src
Kyösti Mälkki d113190d23 AMD k8 fam10: Fix romstage handoff
It is not possible for cbmem_add() to complete succesfully before
cbmem_recovery() is called. Adding more tables on S3 resume path
is also not possible.

Change-Id: Ic14857eeef2932562acee4a36f59c22ff4ca1a84
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15472
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-10 04:03:09 +02:00
..
acpi
arch acpi: Change device properties to work as a tree 2016-07-08 17:21:26 +02:00
commonlib region: Add writeat and eraseat support 2016-06-24 20:48:12 +02:00
console console/post: be explicit about conditional cmos_post_log() compiling 2016-05-25 18:04:11 +02:00
cpu AMD k8 fam10: Fix romstage handoff 2016-07-10 04:03:09 +02:00
device device: i2c: Add support for I2C bus operations 2016-06-09 17:05:40 +02:00
drivers drivers/i2c/da7219: Add driver for generating device in SSDT 2016-07-08 17:22:16 +02:00
ec google/chromeec: Update EC command header 2016-07-10 03:54:07 +02:00
include lib/gpio: add pullup & pulldown gpio_base2_value() variants 2016-07-07 20:44:36 +02:00
lib lib/gpio: add pullup & pulldown gpio_base2_value() variants 2016-07-07 20:44:36 +02:00
mainboard gru: include ram_code in coreboot table 2016-07-10 03:53:57 +02:00
northbridge nb/intel/x4x: Fix underclocking of 800MHz DDR2 RAM 2016-07-09 13:49:00 +02:00
soc soc/intel/quark: Pass in the memory initialization parameters 2016-07-08 17:59:20 +02:00
southbridge PCI: Use PCI_DEVFN macro instead of DEV_FUNC 2016-07-06 21:58:09 +02:00
superio sio/winbond/w83667hg-a: Add pinmux defines for UART B 2016-05-29 19:34:54 +02:00
vendorcode soc/intel/quark: Pass in the memory initialization parameters 2016-07-08 17:59:20 +02:00
Kconfig Kconfig: Show DEBUG_BOOT_STATE in the Debug menu 2016-07-01 21:33:36 +02:00