Julius Werner d0db3a90ad vboot2: Reduce minimum required work buffer size ... Apparently our initial submission of 16K was a little too generous for the vboot2 work buffer, and I hear that we should also be well within bounds for 12K. This patch reduces the minimum asserted by memlayout so some of our low-mem boards can get a few more kilobytes back for discretionary spending. Also changes the required minimum alignment to 8 since that's what the current vboot code aligns it to anyway, and add a warning comment to make it clearer that this is a dangerous number people should not be playing with lightly. BRANCH=None BUG=None TEST=Built and booted on Pinky. Original-Change-Id: Iae9c74050500a315c90f5d5517427d755ac1dfea Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/232613 Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 64e972f103) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I362b8c33cf79534bb76bd7acda44d467563fe133 Reviewed-on: http://review.coreboot.org/9445 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)		2015-04-10 16:49:02 +02:00
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amd	vendorcode/amd/agesa/f16kb: Enable support for AM1 socket	2015-04-10 15:29:24 +02:00
google	vboot2: Reduce minimum required work buffer size	2015-04-10 16:49:02 +02:00
intel	intel/rangeley: Update UPD_DATA_REGION to support POST-GOLD 2 FSP	2015-01-31 23:09:26 +01:00
Kconfig	AMD Steppe Eagle: Add binary PI vendorcode files	2014-08-30 19:13:45 +02:00
Makefile.inc	Add Intel FSP northbridge support Sandybridge and Ivybridge	2013-12-04 18:45:13 +01:00