Stefan Reinauer 5a559d4386 The UART2 on the AMD cs5536 is incorrectly configured in two places. ... GPIO lines 4 and 3 are swapped and also incorrectly put in IR mode receive (compound fault). Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Edwin Beasant <edwin_beasant@virtensys.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5074 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1		2010-02-03 13:49:24 +00:00
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amd	The UART2 on the AMD cs5536 is incorrectly configured in two places.	2010-02-03 13:49:24 +00:00
broadcom	coreboot used to have two different "APIs" for memory accesses:	2010-01-16 17:53:38 +00:00
intel	Move all IOAPIC selection to southbridges, and remove them	2010-01-18 17:30:36 +00:00
nvidia	Move all IOAPIC selection to southbridges, and remove them	2010-01-18 17:30:36 +00:00
ricoh	minimal whitespace fix (trivial)	2009-10-22 17:02:44 +00:00
sis	Move all IOAPIC selection to southbridges, and remove them	2010-01-18 17:30:36 +00:00
ti	Add support for the Texas Instruments Cardbus+Firewire bridge TI PCI7420	2010-01-17 13:52:50 +00:00
via	Move all IOAPIC selection to southbridges, and remove them	2010-01-18 17:30:36 +00:00
Kconfig	Add support for the Texas Instruments Cardbus+Firewire bridge TI PCI7420	2010-01-17 13:52:50 +00:00
Makefile.inc	Add support for the Texas Instruments Cardbus+Firewire bridge TI PCI7420	2010-01-17 13:52:50 +00:00