coreboot/configs/config.baskingridge
Aaron Durbin 99a82f0a6d coreboot: update haswell configs
Now that CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM is
an option the haswell boards need to be kept in line
to maintain their previous behavior. This commit
is separated from the actual implementation for
easier rebasing.

BUG=None
BRANCH=None
TEST=Built for falco.
CQ-DEPEND=CL:172602

Change-Id: Ic8b1c7f37ab4ac7b7d453e924c30f18a528f6eb6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172643
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
2013-10-11 23:27:04 +00:00

35 lines
1.1 KiB
Text

CONFIG_COLLECT_TIMESTAMPS=y
CONFIG_USE_BLOBS=y
CONFIG_VENDOR_INTEL=y
CONFIG_BOARD_INTEL_BASKING_RIDGE=y
CONFIG_HAVE_MRC=y
CONFIG_MRC_FILE="/build/fox_baskingridge/firmware/mrc.bin"
CONFIG_CBFS_SIZE=0x100000
CONFIG_CONSOLE_CBMEM=y
# CONFIG_CONSOLE_SERIAL is not set
# CONFIG_PCI_ROM_RUN is not set
# CONFIG_ON_DEVICE_ROM_RUN is not set
# CONFIG_S3_VGA_ROM_RUN is not set
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_114=y
CONFIG_FRAMEBUFFER_KEEP_VESA_MODE=y
CONFIG_VGA_BIOS_ID="8086,0416"
CONFIG_VGA_BIOS=y
CONFIG_VGA_BIOS_FILE="3rdparty/mainboard/intel/baskingridge/vgabios.bin"
CONFIG_CPU_ADDR_BITS=36
CONFIG_CACHE_ROM=y
CONFIG_MARK_GRAPHICS_MEM_WRCOMB=y
CONFIG_ELOG=y
CONFIG_ELOG_GSMI=y
CONFIG_ELOG_BOOT_COUNT=y
CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET=144
CONFIG_SPI_FLASH_SMM=y
CONFIG_CMOS_POST=y
CONFIG_CMOS_POST_OFFSET=0x70
CONFIG_RELOCATABLE_RAMSTAGE=y
CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM=y
CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE=y
CONFIG_VBOOT_VERIFY_FIRMWARE=y
CONFIG_FLASHMAP_OFFSET=0x00610000
# CONFIG_MULTIBOOT is not set
CONFIG_PAYLOAD_NONE=y