Subrata Banik cffc938934 soc/intel/alderlake: Create separate Kconfig for CLKSRC and CLKREQ ... As per Hardware Architecture Specification (HAS) ADL-P has 7 CLKSRC and 10 CLKREQ (7 SRCCLK is internal and 3 SRCCLK from external CLK chip). ADL-M has 6 SRCCLK and CLKREQ (no external CLK chip). Change-Id: I7d223c165f819669722cbc80245fa8ec20372352 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50130 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2021-02-01 08:55:34 +00:00
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acpi	ACPI: Do minor improvements on GNVS	2021-01-29 10:21:25 +00:00
arch	arch/x86/smbios: Add Number Of Power Cords field to be overriden	2021-02-01 08:50:48 +00:00
commonlib
console
cpu	sb/intel/i82801gx,ix: Drop MPEN from GNVS	2021-02-01 08:54:31 +00:00
device	device/oprom/include/x86emu/fpu_regs.h: Fix lint error	2021-02-01 08:46:11 +00:00
drivers	bayhub bh720: Add helpers to access PCR registers	2021-02-01 08:54:45 +00:00
ec	ec/google/wilco: Convert to ASL 2.0 syntax	2021-01-24 21:51:39 +00:00
include	include/device/pci_ids.h: Add Cannon Lake PCH-H SATA dev ID	2021-02-01 08:52:34 +00:00
lib	lib/asan.c: Update SPDX license	2021-02-01 08:53:22 +00:00
mainboard	soc/intel/alderlake: Create separate Kconfig for CLKSRC and CLKREQ	2021-02-01 08:55:34 +00:00
northbridge	nb/intel/haswell: Calculate TSEG limit from registers	2021-02-01 08:50:24 +00:00
security	security/vboot: Add config for GBB_FLAG_ENABLE_UDC	2021-02-01 08:55:22 +00:00
soc	soc/intel/alderlake: Create separate Kconfig for CLKSRC and CLKREQ	2021-02-01 08:55:34 +00:00
southbridge	sb/intel/i82801gx,ix: Drop MPEN from GNVS	2021-02-01 08:54:31 +00:00
superio	superio/nuvoton/common/Kconfig: Remove HWM config	2021-01-29 09:39:43 +00:00
vendorcode	vc/google/chromeos/Kconfig: Remove unused NO_TPM_RESUME	2021-01-29 09:40:19 +00:00
Kconfig