Raul E Rangel 21fdd44db0 soc/amd/cezanne,vc/cezanne: Implement svc_write_postcode ... This will allow verstage to write post codes. BUG=b:215425753 TEST=Boot guybrush and verify PSP post codes are printed 22-01-31 15:12:03.214 (S3->S0) 22-01-31 15:12:03.214 03 04 0f 0e f0 f1 f2 01 10 a0 a2 <--new Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I6ceee8fcb094f462de99c07aef8e96425d9c3270 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61522 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2022-02-02 22:56:43 +00:00
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amd	soc/amd/cezanne,vc/cezanne: Implement svc_write_postcode	2022-02-02 22:56:43 +00:00
cavium	src: use ARRAY_SIZE where possible	2021-02-15 11:30:40 +00:00
eltan	src/vendorcode/eltan: Don't reference CONFIG_CBFS_SIZE	2021-07-28 08:19:30 +00:00
google	chromeos: Add an elog for Chrome OS diagnostic boot	2022-01-11 23:44:51 +00:00
intel	vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2511_04	2022-01-13 18:04:13 +00:00
mediatek	vc/mediatek/mt8195: Fix rank1 CKE setting for single-rank DRAM	2021-12-01 09:48:17 +00:00
siemens	cbfs: Simplify load/map API names, remove type arguments	2020-12-02 22:13:17 +00:00
Makefile.inc	soc/mediatek/mt8192: initialize DRAM using vendor reference code	2021-03-08 03:15:43 +00:00