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Raul E Rangel cf6dc7d3a1 soc/amd/cezanne: Add root_complex 
This is a copy/paste of picasso with a few things removed. With this
change we can jump into depthcharge.

Allocated resources:
   PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0
   PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
   PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 2
   PCI: 00:00.0 resource base 100000 size 1f00000 align 0 gran 0 limit 0 flags e0004200 index 3
   PCI: 00:00.0 resource base 2000000 size 1c0000 align 0 gran 0 limit 0 flags f0004200 index 4
   PCI: 00:00.0 resource base 21c0000 size cde40000 align 0 gran 0 limit 0 flags e0004200 index 5
   PCI: 00:00.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
   PCI: 00:00.0 resource base 100000000 size 30e340000 align 0 gran 0 limit 0 flags e0004200 index 6
   PCI: 00:00.0 resource base 40e340000 size cc0000 align 0 gran 0 limit 0 flags f0004200 index 7
   PCI: 00:00.0 resource base 40f000000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index 8
   PCI: 00:00.0 resource base 410000000 size 20000000 align 0 gran 0 limit 0 flags f0004200 index 9
   PCI: 00:00.0 resource base cfffe000 size 2000 align 0 gran 0 limit 0 flags f0004200 index a
   PCI: 00:00.0 resource base ceffe000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index b

TEST=Boot majolica and see depthcharge finally loading:
Starting depthcharge on MAJOLICA...
new_rt5682_codec: chip = 0x1A
Looking for NVMe Controller 0x3004cac8 @ 00:01:07

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I52682ec2a06c7e219c221648f241e18e26a9358e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50339
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-09 21:29:59 +00:00
..
acpi acpi: Add support for reporting CrashLog in BERT table 2021-02-04 10:21:02 +00:00
arch arch/x86/cpu.c: Remove redundant <arch/cpu.h> 2021-02-07 22:02:26 +00:00
commonlib acpi: Add support for reporting CrashLog in BERT table 2021-02-04 10:21:02 +00:00
console lib/trace: Remove TRACE support 2020-12-02 23:35:58 +00:00
cpu mb/emulation/qemu: Fix SMP boot 2021-02-04 09:53:02 +00:00
device soc/intel/broadwell: Conditionally skip PRE_GRAPHICS_DELAY 2021-02-06 07:33:51 +00:00
drivers soc/amd,intel: Drop s3_resume parameter on FSP-S functions 2021-02-09 07:53:23 +00:00
ec src/ec/acpi/ec.asl: Convert to ASL 2.0 2021-02-09 07:46:40 +00:00
include src: Add missing <cbmem.h> 2021-02-09 15:26:51 +00:00
lib drivers/intel/fsp1_1,fsp2_0: Refactor logo display 2021-02-09 07:52:31 +00:00
mainboard drivers/intel/fsp1_1,fsp2_0: Refactor logo display 2021-02-09 07:52:31 +00:00
northbridge nb/intel/x4x: Constify write leveling arrays 2021-02-07 22:36:57 +00:00
security security/vboot/bootmode: Add weak fill_lb_gpios 2021-02-09 20:43:12 +00:00
soc soc/amd/cezanne: Add root_complex 2021-02-09 21:29:59 +00:00
southbridge sb/intel/i82801{dx,ix,jx}/lpc.c: Fix typo in comment 2021-02-09 07:48:24 +00:00
superio superio/nuvoton/common/Kconfig: Remove HWM config 2021-01-29 09:39:43 +00:00
vendorcode vc/amd/fsp/cezanne: add FspGuids.h 2021-02-09 19:13:29 +00:00
Kconfig nb/intel/gm45: Factor out {DMI,EP,MCH}BAR accessors 2021-02-07 20:20:00 +00:00