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coreboot/src/soc/intel
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Zhuohao Lee b8b40964fc mb, soc: Add the SPD_CACHE_ENABLE 
In order to cache the spd data which reads from the memory module, we
add SPD_CACHE_ENABLE option to enable the cache for the spd data. If
this option is enabled, the RW_SPD_CACHE region needs to be added to
the flash layout for caching the data.
Since the user may remove the memory module after the bios caching the
data, we need to add the invalidate flag to invalidate the mrc cache.
Otherwise, the bios will use the mrc cache and can make the device
malfunction.

BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=build pass and enable this feature to the brask
     the device could speed up around 150ms with this feature.

Change-Id: If7625a00c865dc268e2a22efd71b34b40c40877b
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62294
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-02 13:10:21 +00:00
..
alderlake mb, soc: Add the SPD_CACHE_ENABLE 2022-03-02 13:10:21 +00:00
apollolake arch/x86: factor out and commonize HPET_BASE_ADDRESS definition 2022-02-25 17:42:45 +00:00
baytrail arch/x86: consolidate HPET base address definitions 2022-02-25 17:44:11 +00:00
braswell arch/x86: consolidate HPET base address definitions 2022-02-25 17:44:11 +00:00
broadwell arch/x86: consolidate HPET base address definitions 2022-02-25 17:44:11 +00:00
cannonlake intelblocks/pcie: Correct mapping between LCAP port and coreboot index 2022-02-25 18:59:51 +00:00
common mb, soc: Add the SPD_CACHE_ENABLE 2022-03-02 13:10:21 +00:00
denverton_ns soc/intel/denverton/include/iomap: drop unused DEFAULT_HPET_ADDR define 2022-02-25 17:43:11 +00:00
elkhartlake intelblocks/pcie: Correct mapping between LCAP port and coreboot index 2022-02-25 18:59:51 +00:00
icelake arch/x86: factor out and commonize HPET_BASE_ADDRESS definition 2022-02-25 17:42:45 +00:00
jasperlake intelblocks/pcie: Correct mapping between LCAP port and coreboot index 2022-02-25 18:59:51 +00:00
quark drivers/fsp/fsp2_0: Rework FSP Notify Phase API configs 2022-02-18 20:21:45 +00:00
skylake intelblocks/pcie: Correct mapping between LCAP port and coreboot index 2022-02-25 18:59:51 +00:00
tigerlake mb, soc: Add the SPD_CACHE_ENABLE 2022-03-02 13:10:21 +00:00
xeon_sp cpu,mb,nb,soc: use HPET_BASE_ADDRESS instead of magic number 2022-02-25 17:44:45 +00:00
Kconfig
Makefile.inc soc/intel/common/cse: Add support for stitching CSE components 2021-10-19 16:09:08 +00:00