1eeb1da1df
Haswell was the original chipset to store the cache
in another area besides CBMEM. However, it was specific
to the implementation. Instead, provide a generic way
to obtain the location of the ramstage cache. This option
is selected using the CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
Kconfig option.
BUG=chrome-os-partner:23249
BRANCH=None
TEST=Built and booted with baytrail support. Also built for
falco successfully.
CQ-DEPEND=CL:172643
CQ-DEPEND=CL:*146397
CQ-DEPEND=CL:*146398
CQ-DEPEND=CL:*146435
CQ-DEPEND=CL:*146445
Change-Id: I70d0940f7a8f73640c92a75fd22588c2c234241b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172602
Reviewed-by: Stefan Reinauer <reinauer@google.com>
|
||
|---|---|---|
| .. | ||
| car | ||
| ep80579 | ||
| fit | ||
| haswell | ||
| hyperthreading | ||
| microcode | ||
| model_6bx | ||
| model_6dx | ||
| model_6ex | ||
| model_6fx | ||
| model_6xx | ||
| model_65x | ||
| model_67x | ||
| model_68x | ||
| model_69x | ||
| model_106cx | ||
| model_206ax | ||
| model_1067x | ||
| model_f0x | ||
| model_f1x | ||
| model_f2x | ||
| model_f3x | ||
| model_f4x | ||
| slot_1 | ||
| slot_2 | ||
| socket_441 | ||
| socket_BGA956 | ||
| socket_FC_PGA370 | ||
| socket_LGA771 | ||
| socket_LGA775 | ||
| socket_mFCBGA479 | ||
| socket_mFCPGA478 | ||
| socket_mPGA478 | ||
| socket_mPGA479M | ||
| socket_mPGA603 | ||
| socket_mPGA604 | ||
| socket_PGA370 | ||
| socket_rPGA989 | ||
| speedstep | ||
| thermal_monitoring | ||
| turbo | ||
| Kconfig | ||
| Makefile.inc | ||