Angel Pons ceca5dedbc device/pci_device.c: Reuse irq variable ... The `irq` variable has the same value as `pIntAtoD[line - 1]`. Change-Id: Iabf760adbc3014b32cfe6f908dc04c38b71bd980 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>		2021-07-01 09:39:56 +00:00
..
acpi	ACPI: Refactor use of global and device NVS	2021-06-14 19:45:56 +00:00
arch	SMBIOS: Introduce smbios_full_table_len function	2021-07-01 07:38:00 +00:00
commonlib	commonlib: Add Intel-specific timestamps for before/after sending EOP	2021-06-30 22:20:32 +00:00
console	Asm code: Use NO_EARLY_BOOTBLOCK_POSTCODES to remove Asm port80s	2021-06-25 15:51:20 +00:00
cpu	src: Move select ARCH_X86 to platforms	2021-06-30 04:48:59 +00:00
device	device/pci_device.c: Reuse irq variable	2021-07-01 09:39:56 +00:00
drivers	SMBIOS: Drop now-unnecessary unions	2021-07-01 07:38:32 +00:00
ec	ec/google: Use EC_HOST_EVENT_NONE	2021-06-30 04:57:16 +00:00
include	SMBIOS: Drop now-unnecessary unions	2021-07-01 07:38:32 +00:00
lib	nvs: Add Chrome OS NVS (CNVS) information to coreboot tables	2021-06-18 18:38:14 +00:00
mainboard	mb/emulation/qemu-i440fx/fw_cfg.c: Use smbios_header	2021-07-01 07:38:18 +00:00
northbridge	nb/intel/haswell/pcie.c: Avoid needless death	2021-06-22 04:47:20 +00:00
security	vboot: add VBOOT_X86_SHA256_ACCELERATION config	2021-07-01 09:38:19 +00:00
soc	soc/intel/alderlake: Select VBOOT_X86_SHA256_ACCELERATION config	2021-07-01 09:38:31 +00:00
southbridge	southbridge/intel/common: Move invalid PIRQ value to 0	2021-06-29 21:50:35 +00:00
superio	src: Retype option API to use unsigned integers	2021-05-06 14:48:15 +00:00
vendorcode	vc/mediatek/mt8195: Fix license headers	2021-06-30 02:22:56 +00:00
Kconfig	option: Allow mainboards to implement the API	2021-05-28 11:37:25 +00:00