erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions
coreboot/src
History
Krzysztof Sywula cdeb41482a soc/intel/common/block: Add WhiskeyLake W0 CPUID 
TEST=Boot up with W0 stepping processor.

Change-Id: Ia7bcfd5235e57c70aa3f15d0042da8b16cf7e186
Signed-off-by: Krzysztof Sywula <krzysztof.m.sywula@intel.com>
Reviewed-on: https://review.coreboot.org/27500
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-18 07:55:51 +00:00
..
acpi
arch riscv: add support for modifying compiler options 2018-07-17 18:09:43 +00:00
commonlib src/{arch,commonlib,cpu}: Use "foo *bar" instead of "foo* bar" 2018-07-09 09:26:18 +00:00
console arch/x86: Drop leftover ROMCC console support 2018-06-08 03:31:12 +00:00
cpu src/{arch,commonlib,cpu}: Use "foo *bar" instead of "foo* bar" 2018-07-09 09:26:18 +00:00
device pnp_device: improve readability 2018-07-17 18:06:19 +00:00
drivers security/vboot: Add interface for FSP 2.0 mrc caching 2018-07-17 17:40:33 +00:00
ec src/{ec,include,lib}: Use "foo *bar" instead of "foo* bar" 2018-07-09 09:28:35 +00:00
include pnp_device: improve readability 2018-07-17 18:06:19 +00:00
lib Coverity: Fix CID1393979 2018-07-12 15:21:10 +00:00
mainboard Add VBT data for Gigabyte GA-H61-S2PV 2018-07-17 11:40:51 +00:00
northbridge nb/i945/raminit: Correct C0DRAMW & C1DRAMW for 4 DIMMs 2018-07-12 11:52:52 +00:00
security security/vboot: Add interface for FSP 2.0 mrc caching 2018-07-17 17:40:33 +00:00
soc soc/intel/common/block: Add WhiskeyLake W0 CPUID 2018-07-18 07:55:51 +00:00
southbridge Kconfig: Make the EM100 config option common 2018-07-16 07:41:14 +00:00
superio superio: move files to match the common naming scheme 2018-07-06 16:47:21 +00:00
vendorcode vendorcode/cavium/include: Make bdk_pop and dpop static 2018-07-17 11:38:28 +00:00
Kconfig Kconfig: Make the EM100 config option common 2018-07-16 07:41:14 +00:00