524 lines
21 KiB
C
524 lines
21 KiB
C
/*
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* $Id$
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*
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* PCI defines and function prototypes
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* Copyright 1994, Drew Eckhardt
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* Copyright 1997--1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
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*
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* For more information, please consult the following manuals (look at
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* http://www.pcisig.com/ for how to get them):
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*
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* PCI BIOS Specification
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* PCI Local Bus Specification
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* PCI to PCI Bridge Specification
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* PCI System Design Guide
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*/
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#ifndef PCI_H
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#define PCI_H
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/*
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* Under PCI, each device has 256 bytes of configuration address space,
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* of which the first 64 bytes are standardized as follows:
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*/
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#define PCI_VENDOR_ID 0x00 /* 16 bits */
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#define PCI_DEVICE_ID 0x02 /* 16 bits */
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#define PCI_COMMAND 0x04 /* 16 bits */
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#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
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#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
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#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
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#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
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#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
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#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
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#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
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#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
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#define PCI_COMMAND_SERR 0x100 /* Enable SERR */
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#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
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#define PCI_STATUS 0x06 /* 16 bits */
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#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
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#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
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#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
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#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
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#define PCI_STATUS_PARITY 0x100 /* Detected parity error */
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#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
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#define PCI_STATUS_DEVSEL_FAST 0x000
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#define PCI_STATUS_DEVSEL_MEDIUM 0x200
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#define PCI_STATUS_DEVSEL_SLOW 0x400
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#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
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#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
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#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
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#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
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#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
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#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
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revision */
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#define PCI_REVISION_ID 0x08 /* Revision ID */
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#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
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#define PCI_CLASS_DEVICE 0x0a /* Device class */
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#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
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#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
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#define PCI_HEADER_TYPE 0x0e /* 8 bits */
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#define PCI_HEADER_TYPE_NORMAL 0
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#define PCI_HEADER_TYPE_BRIDGE 1
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#define PCI_HEADER_TYPE_CARDBUS 2
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#define PCI_BIST 0x0f /* 8 bits */
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#define PCI_BIST_CODE_MASK 0x0f /* Return result */
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#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
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#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
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/*
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* Base addresses specify locations in memory or I/O space.
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* Decoded size can be determined by writing a value of
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* 0xffffffff to the register, and reading it back. Only
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* 1 bits are decoded.
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*/
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#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
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#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
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#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
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#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
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#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
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#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
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#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
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#define PCI_BASE_ADDRESS_SPACE_IO 0x01
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#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
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#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
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#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
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#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
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#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
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#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
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#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
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#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
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/* bit 1 is reserved if address_space = 1 */
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/* Header type 0 (normal devices) */
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#define PCI_CARDBUS_CIS 0x28
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#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
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#define PCI_SUBSYSTEM_ID 0x2e
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#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
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#define PCI_ROM_ADDRESS_ENABLE 0x01
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#define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
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#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
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/* 0x35-0x3b are reserved */
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#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
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#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
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#define PCI_MIN_GNT 0x3e /* 8 bits */
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#define PCI_MAX_LAT 0x3f /* 8 bits */
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/* Header type 1 (PCI-to-PCI bridges) */
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#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
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#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
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#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
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#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
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#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
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#define PCI_IO_LIMIT 0x1d
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#define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */
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#define PCI_IO_RANGE_TYPE_16 0x00
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#define PCI_IO_RANGE_TYPE_32 0x01
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#define PCI_IO_RANGE_MASK ~0x0f
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#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
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#define PCI_MEMORY_BASE 0x20 /* Memory range behind */
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#define PCI_MEMORY_LIMIT 0x22
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#define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
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#define PCI_MEMORY_RANGE_MASK ~0x0f
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#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
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#define PCI_PREF_MEMORY_LIMIT 0x26
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#define PCI_PREF_RANGE_TYPE_MASK 0x0f
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#define PCI_PREF_RANGE_TYPE_32 0x00
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#define PCI_PREF_RANGE_TYPE_64 0x01
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#define PCI_PREF_RANGE_MASK ~0x0f
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#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
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#define PCI_PREF_LIMIT_UPPER32 0x2c
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#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
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#define PCI_IO_LIMIT_UPPER16 0x32
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/* 0x34 same as for htype 0 */
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/* 0x35-0x3b is reserved */
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#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
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/* 0x3c-0x3d are same as for htype 0 */
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#define PCI_BRIDGE_CONTROL 0x3e
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#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
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#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
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#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
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#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
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#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
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#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
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#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
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/* Header type 2 (CardBus bridges) */
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#define PCI_CB_CAPABILITY_LIST 0x14
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/* 0x15 reserved */
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#define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
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#define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
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#define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
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#define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
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#define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
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#define PCI_CB_MEMORY_BASE_0 0x1c
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#define PCI_CB_MEMORY_LIMIT_0 0x20
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#define PCI_CB_MEMORY_BASE_1 0x24
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#define PCI_CB_MEMORY_LIMIT_1 0x28
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#define PCI_CB_IO_BASE_0 0x2c
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#define PCI_CB_IO_BASE_0_HI 0x2e
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#define PCI_CB_IO_LIMIT_0 0x30
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#define PCI_CB_IO_LIMIT_0_HI 0x32
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#define PCI_CB_IO_BASE_1 0x34
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#define PCI_CB_IO_BASE_1_HI 0x36
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#define PCI_CB_IO_LIMIT_1 0x38
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#define PCI_CB_IO_LIMIT_1_HI 0x3a
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#define PCI_CB_IO_RANGE_MASK ~0x03
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/* 0x3c-0x3d are same as for htype 0 */
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#define PCI_CB_BRIDGE_CONTROL 0x3e
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#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
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#define PCI_CB_BRIDGE_CTL_SERR 0x02
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#define PCI_CB_BRIDGE_CTL_ISA 0x04
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#define PCI_CB_BRIDGE_CTL_VGA 0x08
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#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
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#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
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#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
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#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
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#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
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#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
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#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
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#define PCI_CB_SUBSYSTEM_ID 0x42
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#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
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/* 0x48-0x7f reserved */
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/* Capability lists */
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#define PCI_CAP_LIST_ID 0 /* Capability ID */
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#define PCI_CAP_ID_PM 0x01 /* Power Management */
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#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
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#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
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#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
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#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
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#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
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#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
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#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
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#define PCI_CAP_SIZEOF 4
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/* Power Management Registers */
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#define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
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#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
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#define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */
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#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
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#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
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#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
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#define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
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#define PCI_PM_CTRL 4 /* PM control and status register */
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#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
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#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
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#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
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#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
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#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
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#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
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#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
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#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
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#define PCI_PM_DATA_REGISTER 7 /* (??) */
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#define PCI_PM_SIZEOF 8
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/* AGP registers */
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#define PCI_AGP_VERSION 2 /* BCD version number */
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#define PCI_AGP_RFU 3 /* Rest of capability flags */
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#define PCI_AGP_STATUS 4 /* Status register */
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#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
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#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
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#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
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#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
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#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
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#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
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#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
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#define PCI_AGP_COMMAND 8 /* Control register */
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#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
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#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
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#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
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#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
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#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
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#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
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#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */
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#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */
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#define PCI_AGP_SIZEOF 12
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/* Slot Identification */
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#define PCI_SID_ESR 2 /* Expansion Slot Register */
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#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
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#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
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#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
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/* Message Signalled Interrupts registers */
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#define PCI_MSI_FLAGS 2 /* Various flags */
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#define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
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#define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
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#define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
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#define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
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#define PCI_MSI_RFU 3 /* Rest of capability flags */
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#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
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#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
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#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
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#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
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/*
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* The PCI interface treats multi-function devices as independent
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* devices. The slot/function address of each device is encoded
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* in a single byte as follows:
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*
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* 7:3 = slot
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* 2:0 = function
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*/
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#define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
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#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
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#define PCI_FUNC(devfn) ((devfn) & 0x07)
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#include <types.h>
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/*
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* There is one pci_dev structure for each slot-number/function-number
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* combination:
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*/
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struct pci_dev {
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struct pci_bus *bus; /* bus this device is on */
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struct pci_dev *sibling; /* next device on this bus */
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struct pci_dev *next; /* chain of all devices */
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void *sysdata; /* hook for sys-specific extension */
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struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
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unsigned int devfn; /* encoded device & function index */
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unsigned short vendor;
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unsigned short device;
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unsigned int class; /* 3 bytes: (base,sub,prog-if) */
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unsigned int hdr_type; /* PCI header type */
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unsigned int master : 1; /* set if device is master capable */
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u8 command;
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/*
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* In theory, the irq level can be read from configuration
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* space and all would be fine. However, old PCI chips don't
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* support these registers and return 0 instead. For example,
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* the Vision864-P rev 0 chip can uses INTA, but returns 0 in
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* the interrupt line and pin registers. pci_init()
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* initializes this field with the value at PCI_INTERRUPT_LINE
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* and it is the job of pcibios_fixup() to change it if
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* necessary. The field must not be 0 unless the device
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* cannot generate interrupts at all.
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*/
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unsigned int irq; /* irq generated by this device */
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/* Base registers for this device, can be adjusted by
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* pcibios_fixup() as necessary.
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*/
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unsigned long base_address[6];
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unsigned long size[6];
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unsigned long rom_address;
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};
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struct pci_bus {
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struct pci_bus *parent; /* parent bus this bridge is on */
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struct pci_bus *children; /* chain of P2P bridges on this bus */
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struct pci_bus *next; /* chain of all PCI buses */
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struct pci_dev *self; /* bridge device as seen by parent */
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struct pci_dev *devices; /* devices behind this bridge */
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void *sysdata; /* hook for sys-specific extension */
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struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
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unsigned char number; /* bus number */
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unsigned char primary; /* number of primary bridge */
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unsigned char secondary; /* number of secondary bridge */
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unsigned char subordinate; /* max number of subordinate buses */
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unsigned long mem, prefmem, io; /* amount of mem, prefetch mem,
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* and I/O needed for this bridge.
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* computed by compute_resources,
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* inclusive of all child bridges
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* and devices
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*/
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u32 membase, memlimit;
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u32 prefmembase, prefmemlimit;
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u32 iobase, iolimit;
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};
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extern struct pci_bus pci_root; /* root bus */
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extern struct pci_dev *pci_devices; /* list of all devices */
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/*
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* Error values that may be returned by the PCI bios.
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*/
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#define PCIBIOS_SUCCESSFUL 0x00
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#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
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#define PCIBIOS_BAD_VENDOR_ID 0x83
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#define PCIBIOS_DEVICE_NOT_FOUND 0x86
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#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
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#define PCIBIOS_SET_FAILED 0x88
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#define PCIBIOS_BUFFER_TOO_SMALL 0x89
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/* Low-level architecture-dependent routines */
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int pcibios_present (void);
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void pcibios_init(void);
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void pcibios_fixup(void);
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void pcibios_fixup_bus(struct pci_bus *);
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char *pcibios_setup (char *str);
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int pcibios_read_config_byte (unsigned char bus, unsigned char dev_fn,
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unsigned char where, u8 *val);
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int pcibios_read_config_word (unsigned char bus, unsigned char dev_fn,
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unsigned char where, u16 *val);
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int pcibios_read_config_dword (unsigned char bus, unsigned char dev_fn,
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unsigned char where, u32 *val);
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int pcibios_write_config_byte (unsigned char bus, unsigned char dev_fn,
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unsigned char where, u8 val);
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int pcibios_write_config_word (unsigned char bus, unsigned char dev_fn,
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unsigned char where, u16 val);
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int pcibios_write_config_dword (unsigned char bus, unsigned char dev_fn,
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unsigned char where, u32 val);
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int pcibios_debugwrite_config_byte (unsigned char bus, unsigned char dev_fn,
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unsigned char where, u8 val);
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int pcibios_debugwrite_config_word (unsigned char bus, unsigned char dev_fn,
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unsigned char where, u16 val);
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int pcibios_debugwrite_config_dword (unsigned char bus, unsigned char dev_fn,
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unsigned char where, u32 val);
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/* Don't use these in new code, use pci_find_... instead */
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int pcibios_find_class (unsigned int class_code, unsigned short index, unsigned char *bus, unsigned char *dev_fn);
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int pcibios_find_device (unsigned short vendor, unsigned short dev_id,
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unsigned short index, unsigned char *bus,
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unsigned char *dev_fn);
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/* Generic PCI interface functions */
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void pci_init(void);
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void pci_setup(char *str, int *ints);
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void pci_quirks_init(void);
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unsigned int pci_scan_bus(struct pci_bus *bus);
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struct pci_bus *pci_scan_peer_bridge(int bus);
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void pci_proc_init(void);
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void proc_old_pci_init(void);
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int get_pci_list(char *buf);
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int pci_proc_attach_device(struct pci_dev *dev);
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int pci_proc_detach_device(struct pci_dev *dev);
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struct pci_dev *pci_find_device (unsigned int vendor, unsigned int device, struct pci_dev *from);
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struct pci_dev *pci_find_class (unsigned int class, struct pci_dev *from);
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struct pci_dev *pci_find_slot (unsigned int bus, unsigned int devfn);
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#define pci_present pcibios_present
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int pci_read_config_byte(struct pci_dev *dev, u8 where, u8 *val);
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int pci_read_config_word(struct pci_dev *dev, u8 where, u16 *val);
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int pci_read_config_dword(struct pci_dev *dev, u8 where, u32 *val);
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int pci_write_config_byte(struct pci_dev *dev, u8 where, u8 val);
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int pci_write_config_word(struct pci_dev *dev, u8 where, u16 val);
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int pci_write_config_dword(struct pci_dev *dev, u8 where, u32 val);
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int pci_debugwrite_config_byte(struct pci_dev *dev, u8 where, u8 val);
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int pci_debugwrite_config_word(struct pci_dev *dev, u8 where, u16 val);
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int pci_debugwrite_config_dword(struct pci_dev *dev, u8 where, u32 val);
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void pci_set_master(struct pci_dev *dev);
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void pci_set_method(void);
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void pci_enumerate(void);
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void pci_configure(void);
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void pci_enable(void);
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void pci_zero_irq_settings(void);
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// historical functions ...
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void intel_conf_writeb(unsigned long port, unsigned char value);
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unsigned char intel_conf_readb(unsigned long port);
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#include <kmalloc.h>
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// Rounding for boundaries.
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// Due to some chip bugs, go ahead and roung IO to 16
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#define IO_ALIGN 16
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#define IO_BRIDGE_ALIGN 4096
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#define MEM_ALIGN 4096
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#include <pciconf.h>
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/* linkages from devices of a type (e.g. superio devices)
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* to the actual physical PCI device. This type is used in an array of
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* structs built by NLBConfig.py. We owe this idea to Plan 9.
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*/
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struct superio;
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struct superio_control {
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void (*pre_pci_init)(struct superio *s);
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|
void (*init)(struct superio *s);
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|
void (*finishup)(struct superio *s);
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|
unsigned int defaultport; /* the defaultport. Can be overridden
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|
* by commands in config
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|
*/
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|
// This is the print name for debugging
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|
char *name;
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|
};
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|
|
|
struct com_ports {
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|
unsigned int enable,baud, base, irq;
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|
};
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|
|
|
// lpt port description.
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|
// Note that for many superios you only really need to define the
|
|
// enable.
|
|
struct lpt_ports {
|
|
unsigned int enable, // 1 if this port is enabled
|
|
mode, // pp mode
|
|
base, // IO base of the parallel port
|
|
irq; // irq
|
|
};
|
|
|
|
struct superio {
|
|
struct superio_control *super; // the ops for the device.
|
|
unsigned int port; // if non-zero, overrides the default port
|
|
// com ports. This is not done as an array (yet).
|
|
// We think it's easier to set up from python if it is not an array.
|
|
struct com_ports com1, com2, com3, com4;
|
|
// DMA, if it exists.
|
|
struct lpt_ports lpt1, lpt2;
|
|
/* flags for each device type. Unsigned int. */
|
|
// low order bit ALWAYS means enable. Next bit means to enable
|
|
// LPT is in transition, so we leave this here for the moment.
|
|
// The winbond chips really stretched the way this works.
|
|
// so many functions!
|
|
unsigned int ide, floppy, lpt;
|
|
unsigned int keyboard, cir, game;
|
|
unsigned int gpio1, gpio2, gpio3;
|
|
unsigned int acpi,hwmonitor;
|
|
};
|
|
|
|
struct southbridge;
|
|
|
|
struct southbridge_control {
|
|
void (*pre_pci_init)(struct southbridge *s);
|
|
void (*init)(struct southbridge *s);
|
|
void (*finishup)(struct southbridge *s);
|
|
// this is the vendor and device id
|
|
unsigned int vendor, device;
|
|
// This is the print name for debugging
|
|
char *name;
|
|
};
|
|
|
|
struct southbridge {
|
|
struct pci_dev *device; // the device.
|
|
struct southbridge_control *southbridge; // the ops for the device.
|
|
unsigned int devfn; /* the devfn.
|
|
* if devfn is known, the device can be
|
|
* configured for PCI discovery.
|
|
* this is needed for some devices such as acer m1535
|
|
*/
|
|
/* flags for each device type. Unsigned int. */
|
|
// low order bit ALWAYS means enable. Next bit means to enable
|
|
// DMA, if it exists.
|
|
unsigned int ide;
|
|
};
|
|
|
|
#endif /* PCI_H */
|
|
|
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